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Keywords: IP/RTL Design Lead, Location: Bangalore, Karnataka

Page: 4

Technical Lead I - VLSI PD CAD

Backend or Analog design with minimal supervision Outcomes: * Work as an individual contributor owning any one task of RTL... Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture...

Company: UST
Posted Date: 13 Sep 2025

Principal Product Engineer

Engineer – Memory IP Products Join a growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY..., HBM3/4, GDDR6/7 or similar IPs Verilog RTL design and gate level verification experience Synthesis and STA experience...

Posted Date: 23 Oct 2025

Senior Technologist, ASIC Development Engineering

. SanDisk, a leader in data storage solutions, is seeking talented and experienced ASIC RTL Design Engineers to join our cutting...: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware...

Company: SanDisk
Posted Date: 29 Nov 2025

Technologist, ASIC Development Engineering

/chip level The job would require complete ownership from RTL to GDS for complete SoC Exposure to IP Hardening for blocks.... Job Description Position Overview: We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC...

Company: SanDisk
Posted Date: 25 Nov 2025

Staff/ Senior Staff DFT Engineer

, hierarchical flows, SSN/IJTAG). Lead cross‑functional collaboration with RTL, synthesis, physical design, verification... development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community...

Company: Marvell
Posted Date: 22 Nov 2025

Senior Staff STA Engineer

process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact This position is with Timing signoff...

Company: Marvell
Posted Date: 16 Nov 2025

Associate III - VLSI - SCL

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 31 Oct 2025

XR Systems Technology Architect - All levels

, SoC architecture, NOC, DDR subsystem, LPDDR IP, caches, security, virtual memory, development, RTL design, Computer vision...-architecture Experience (2 to 15 years) in areas covering at least one of the following: IP and SOC design, DV, micro...

Company: Qualcomm
Posted Date: 29 Oct 2025

XR Systems Technology Architect - All levels

architecture, NOC, DDR subsystem, LPDDR IP, caches, security, virtual memory, development, RTL design, Computer vision, Artificial... (10+ years) in areas covering at least one of the following: IP and SOC design, DV, micro architecture, architecture...

Company: Qualcomm
Posted Date: 29 Oct 2025

Associate II - VLSI

to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development • Experience with AMD Vivado & Vitis... • Strong can-do attitude Skills: Fpga Design,Verilog RTL based IP design,System Verilog About Company: UST is a global...

Company: UST
Posted Date: 29 Oct 2025

Senior DFT Engineer, SSG

. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning..., pattern generation, and diagnostics. Design Background - Experience in writing verilog/system verilog RTL related to DFT...

Company: Amazon
Posted Date: 25 Oct 2025

Associate III - VLSI

: REQUIRED: • Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog...,Verilog RTL based IP design,Testbench development About Company: UST is a global digital transformation solutions provider...

Company: UST
Posted Date: 23 Oct 2025

Associate II - VLSI DFTN

of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...

Company: UST
Posted Date: 14 Oct 2025

Associate II - VLSI DFT

of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...

Company: UST
Posted Date: 14 Oct 2025