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Keywords: ASIC RTL Design Technical Lead, Location: San Jose, CA

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ASIC Engineering Technical Leader

industry. Your Impact: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead... with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 05 Feb 2026

ASIC Engineering Technical Leader

: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test.... You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 26 Jan 2026

ASIC Engineering Technical Leader

. Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations. Work... required with at least 10+ years of ASIC Hardware Development experience. Prior experience on hardware design specifications and verification...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 26 Jan 2026

ASIC DFT DV Technical Leader

as a senior DFT verification lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams... Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 26 Jan 2026

ASIC Engineering Program Manager

in Computer Science and/or Electrical Engineering or other technical field. Prior experience in managing ASIC design flow... is filled or if a sufficient number of applications are received. Meet the Team Cisco Silicon One leads Cisco’s ASIC design...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 06 Feb 2026

Senior SoC Design Verification Engineer (remote)

record of all verification strategies Implement coverage tracking and metrics Lead technical projects and mentorship... using SystemVerilog Familiarity with digital design concepts and ASIC development flow Programming experience using C, C...

Location: San Jose, CA
Posted Date: 06 Feb 2026

Manager, FPGA IP Design Engineering

technical direction on IP selection, protocols, and SystemVerilog-based design decisions. Post-Silicon & Validation Ensure..., or ASIC design and verification flows. Experience with DDR, memory controllers, MIPI, or HDMI. Knowledge of memory...

Posted Date: 05 Feb 2026

Physical Design Power Grid/IR/EM Engineer

technical field and 6+ years of hands-on experience in IR /EM analysis, methodology, or physical design for multi-voltage...An ASIC IR/EM (Internal Resistance / Electromigration) Engineer focuses on the physical reliability and power integrity...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Chip Lead

. Deep Technical Reviews Actively review RTL, verification plans, physical design closure, DFT, and test strategy.... Lead Execution to Tapeout Drive technical readiness for tapeout, including: RTL and verification completeness Timing...

Company: Etched
Location: San Jose, CA
Posted Date: 17 Jan 2026
Salary: $2000 per month