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Keywords: Design Engineer/ RTL Engineer, Location: USA

Page: 15

Silicon Design Verification Engineer

and random verification tests. Debug test failures to determine the root cause; work with RTL engineers to resolve design... from Valve. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification...

Posted Date: 24 Jun 2025

ASIC Design Engineer

Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test... cases for the module level and chip level. Participate in FPGA emulation and post-silicon validation. Write design...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 22 Jun 2025
Salary: $120000 - 145000 per year

SoC Design and Integration Engineer

player with good communication skill. This is a great opportunity to join a fast-paced SoC team responsible for RTL Design... with excellent analytical and technical skills. Besides ASIC and/or FPGA design experience, this professional need to be a great team...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 22 Jun 2025
Salary: $115600 - 173400 per year

Senior Staff Engineer, Physical Design

at Marvell. Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence... (place and route, static timing, physical verification) using industry standard EDA tools. Work with RTL design teams...

Company: Marvell
Location: Austin, TX
Posted Date: 22 Jun 2025
Salary: $125900 - 186260 per year

MTS Silicon Design Engineer

, reset verification, and contention checking; RTL Design; and Debugging silicon at test and board level. #LI-DP1..._ Job Role and Responsibility: Xilinx, Inc., a subsidiary of AMD, Inc., is hiring MTS Silicon Design Engineers to Research...

Posted Date: 22 Jun 2025

Senior Principal Digital IC Design Engineer

and define micro-architecture of the design Implement designs using low-power RTL coding techniques Collaborate with the... microprocessors. RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 22 Jun 2025

Principal Engineer, Physical Design

of developing and implementing intricate timing and logic ECOs. Collaboration is key, and you will work closely with the RTL design... logic course and projects that involved circuit design, testing, and timing analysis. Strong understanding of standard RTL...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 17 Jun 2025
Salary: $146850 - 220000 per year

Cellular ASIC Design Integration Engineer

. Strong knowledge of FE tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX). Strong knowledge of RTL design and HDL languages (Verilog...? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design...

Company: Apple
Location: San Diego, CA
Posted Date: 15 Jun 2025

Cellular ASIC Design Integration Engineer

. Strong knowledge of FE tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX). Strong knowledge of RTL design and HDL languages (Verilog...? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 15 Jun 2025

Cellular ASIC Design Integration Engineer

(CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX). Knowledge of RTL design and HDL languages (Verilog, System Verilog...? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 15 Jun 2025
Salary: $121900 - 183600 per year

Cellular ASIC Design Integration Engineer

tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX). Knowledge of RTL design and HDL languages (Verilog, System Verilog...? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design...

Company: Apple
Location: San Diego, CA
Posted Date: 15 Jun 2025

Cellular ASIC Design Integration Engineer

tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX). Knowledge of RTL design and HDL languages (Verilog, System Verilog...? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 15 Jun 2025

Cellular ASIC Design Integration Engineer

(CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX). Knowledge of RTL design and HDL languages (Verilog, System Verilog...? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design...

Company: Apple
Location: San Diego, CA
Posted Date: 15 Jun 2025
Salary: $115700 - 174200 per year

GPU- Physical Design Engineer

process nodes and employing latest design techniques to push PPA envelope which includes working with RTL design teams... gate count design to meet very aggressive Power, Performance and Area (PPA) targets. Involves working on latest technology...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 13 Jun 2025

ASIC Design Engineer

, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector...-architecture and implementation specifications. Implement Verilog RTL to meet timing and performance requirements. Help define...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 12 Jun 2025

Design Engineer Architect/Lead

Technical Skills/ background: The Design Architect/ Lead will lead a small team of engineers to interact with the... customer on aspects including but limited to physical synthesis, influencing RTL content and coding styles that will lend...

Company: Broadcom
Location: Fort Collins, CO
Posted Date: 12 Jun 2025

GPU Design Engineer - Memory Hierarchy

help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll.... Join us to help deliver the next groundbreaking products containing an Apple designed GPU. As part of the GPU Memory Hierarchy Design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 12 Jun 2025

Wireless SoC Design Engineer

team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration... you to apply. Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements...

Company: Apple
Location: Irvine, CA
Posted Date: 11 Jun 2025

CPU Physical Design Pathfinding Engineer

, and Area (PPA) goals. Collaborate with Architecture, RTL, Physical Design, Circuits, CAD, and Post-Silicon teams to drive... innovation and optimization. Key Responsibilities Solve critical CPU implementation challenges across design and CAD teams...

Company: Vaco
Location: San Diego, CA
Posted Date: 10 Jun 2025

Wireless SoC Design Engineer

team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration... you to apply. Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 10 Jun 2025