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Keywords: Design Engineer (Low Power), Location: Santa Clara, CA

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Senior ASIC Physical Design Engineer, Netlisting

, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer... human inventiveness and intelligence. What you'll be doing: You will drive physical design of high-frequency and low...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 08 Jan 2026

Staff Engineer, Analog IC Design

circuits, regulators, and other analog circuits. Knowledge and experience on low power and high speed design techniques...-Signal IC Design Engineer, you will be part of a key team designing highly sophisticated CMOS transceiver/SERDES products...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 10 Dec 2025
Salary: $118900 - 178100 per year

Design Verification Engineer - Principal

, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center Design... that each design meets our customers’ specifications whether they’re a major hyperscaler company or telecom organization...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Mar 2026
Salary: $158600 - 237600 per year

Design Verification Engineer - Senior Principal

, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center Design... that each design meets our customers’ specifications whether they’re a major hyperscaler company or telecom organization...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Mar 2026

CPU Server Physical Design Engineer

design to assist in the development and verification of high performance and low power CPU designs. Identifies and solves... routine problems to ensure design completeness, functionality, power, and performance. Collaborates with team members...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 06 Mar 2026

Design Engineer - Sensors

, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced... flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 02 Mar 2026

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area.... Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 02 Mar 2026

Sr. Staff CPU Physical Design CAD Engineer

design to develop and verify critical high performance and low power CPU designs. Anticipates, identifies, and solves highly... complex problems to ensure design completeness, functionality, power, and performance. Collaborates with cross-functional...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 02 Mar 2026

Staff, Physical Design Engineer

for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic... design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 02 Mar 2026

Senior Design Verification Engineer

Solid understanding of AMBA bus protocols (e.g., AXI, AHB, APB) Knowledge of low-power design concepts and power management..., and emulation, to continuously improve testbench quality and efficiency Own end-to-end low-power verification, including testbench...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 02 Mar 2026

CPU Server Physical Design Engineer

performance and low power CPU designs. Anticipates, identifies, and solves complex problems to ensure design completeness...-offs (e.g., performance, power, cost, functionalities, etc.) in order to accomplish product goals. Evaluates the design...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 01 Mar 2026

Senior ASIC RTL Design Engineer

and low-power RTL techniques. Integrate IP blocks at the subsystem level and resolve inter-IP design and integration issues..., timing closure, and post-silicon validation. Experience with front-end EDA tools, sign-off flows, and low-power design...

Posted Date: 20 Feb 2026

Principal Design Verification Engineer

, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center Design... that each design meets our customers’ specifications whether they’re a major hyperscaler company or telecom organization...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 05 Feb 2026
Salary: $158600 - 237600 per year

Senior Circuit Design Engineer

and Route design tools and datapath Tiling techniques is required. Hands on experience in design and analysis of low power... circuits, e.g. power gating, decaps, multi-vt is required. Understanding of Design-for-test (DFT) and logic design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

Senior ASIC RTL Design Engineer

. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow...: RTL design of high speed design, clock/reset/power features, IP Integration, sub-system level design Architect...

Posted Date: 25 Dec 2025

Principal Interconnect Micro-architect and RTL Design Engineer

bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power... and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team...

Posted Date: 17 Dec 2025

Senior Software Engineer, CUDA Core Libraries

software! We are hiring a full-time Software Engineer to work on the CUDA Core Libraries that power GPU computing for both C... for core CUDA functionality. Compose, optimize, and evolve GPU algorithms and APIs, from high-level interfaces down to low...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 08 Mar 2026

Software Development Engineer, Amazon IVS

. About The Role The IVS Control Plane team is looking for a backend software engineer to design and develop public APIs... world to deliver low-latency, interactive video experiences. Key job responsibilities - Design and develop backend...

Company: Amazon
Location: Santa Clara, CA
Posted Date: 07 Mar 2026

Software Development Engineer, Amazon IVS

. About The Role The IVS Control Plane team is looking for a backend software engineer to design and develop public APIs... world to deliver low-latency, interactive video experiences. Key job responsibilities - Design and develop backend...

Company: Amazon
Location: Santa Clara, CA
Posted Date: 07 Mar 2026

Firmware Engineer, Memory Subsystem - New College Grad 2026

a more exciting time to join our team! We are looking for a Firmware Engineer - New College Grad to join our Memory Subsystem Team...! What you'll be doing: Firmware Design & Execution: Design and implement firmware for the memory subsystem, including silicon...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 06 Mar 2026
Salary: $124000 - 195500 per year