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Keywords: Design Verification Engineer, Location: Santa Clara, CA

Page: 5

CPU Server Physical Design Clock Engineer

Summary: As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block level and top.... Proficiency in SPICE simulation and analysis for circuit design and verification. Preferred qualifications MS in Electrical...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 24 Jul 2025

Senior Physical Design Engineer

We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over two decades... to join our diverse team today. What you'll be doing: Responsible for all aspects of physical design and implementation of GPU...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Jul 2025

Principal Design Engineer

communication in AI clusters. What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL... for micro-architecture design and development of DSP logic. Working with Architects and Verification engineers to deliver...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 19 Jul 2025
Salary: $146850 - 220000 per year

Senior SoC Design Engineer

. Experience in negotiating solutions across design, verification, PD, and IP teams. Experience working with UCIe/CXL/PCIe/D2D... to do their best work. Come join the team and see how you can make a lasting impact on the world. Join NVIDIA as a Senior SoC Design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 16 Jul 2025

ASIC Design Engineer - New College Grad 2025

We are now looking for an ASIC Design Engineer! NVIDIA has been transforming computer graphics, PC gaming... and see how you can make a lasting impact on the world. Join NVIDIA as an ASIC Design Engineer, influencing product lines spanning...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Jul 2025
Salary: $96000 - 184000 per year

IP Design Engineer

wrappers for third party cores, and interface with IP vendors 2. Work with Verification Engineers to verify IP and debug... of experience in digital design RTL coding experience using Verilog and/or System Verilog Strong in digital design, micro...

Company: LanceSoft
Location: Santa Clara, CA
Posted Date: 04 Oct 2025

ASIC Design Engineer - New College Grad 2026

development (Verilog). Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing...NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 04 Oct 2025
Salary: $96000 - 161000 per year

IP Design Engineer

Design and develop Soft IP for FPGAs using Verilog/SystemVerilog Integrate third-party IP cores into FPGA systems... with custom RTL wrappers Collaborate with verification teams to debug and validate IP functionality Support board bring-up...

Posted Date: 03 Oct 2025

Senior Digital Design Engineer - High-Speed I/O and Photonics

, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing... design, proficient with front-end design flow and tools. Deep understanding of Verilog or System Verilog, logic design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Sep 2025

Senior Layout Mask Design Engineer

and verifying against design rules and schematics. Perform power robustness check and EMIR verification and fixes Negotiation.... Strong background with Cadence custom circuit design tools - particularly Virtuoso. Experience running and debugging with verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Sep 2025
Salary: $124000 - 195500 per year

Principal Silicon Design Engineer

experience in reusable verification methodology such as UVM Have hands-on experience in SOC Design/Integration activities... and IP level design, SOC architecture and implementation strategies. THE PERSON: Excellent communication and presentation...

Posted Date: 20 Sep 2025

Senior Digital Design Engineer - High-Speed I/O and Photonics

, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing... design, proficient with front-end design flow and tools. Deep understanding of Verilog or System Verilog, logic design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Sep 2025

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL...Do you have a passion for crafting entirely new solutions? Be a part of a world-class silicon design team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Aug 2025

Senior Principal Analog Mixed-Signal IC Design Engineer

and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc. Should be comfortable carrying... out layout activities in nanometric technologies and be able to supervise physical design. Should be able to work in the...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Aug 2025

Senior Principal Digital IC Design Engineer

microprocessors. RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block...-level functional verification. Experience in implementation/timing closure for high speed design. Hands-on experience...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 15 Aug 2025

Memory Design Engineer

Work on transistor level design of analog and mixed signal circuits in memory (SRAM/DRAM) for display chip or image.... Perform the block level and transistor level layout design using CAD tools like Cadence Virtuoso and Calibre. Collaborate...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 13 Aug 2025
Salary: $156853 - 160000 per year

Memory Design Engineer

Work on detailed transistor level design of analog and mixed signal circuits in memory (DRAM/SRAM) for display chip... with Cadence OrCAD, Altium Designer, and SPICE. Perform the block level and transistor level layout and circuit design. Collaborate...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 13 Aug 2025
Salary: $156853 - 160000 per year

SoC Design Engineer

verification and modeling using SVA, Python, Perl, C++/C, and HLS; Work with sensor digital and analog engineers for system design... level verification and test case design for SoC. SoC IO chip bringup and debug. SoC architecture. Scripting with Python...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 13 Aug 2025
Salary: $151091 - 155000 per year

Senior Staff Analog Mixed-Signal Design Engineer

to ensure successful project execution. Utilize state-of-the-art EDA tools for design automation and verification. Prepare.... Proficient in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Aug 2025
Salary: $140350 - 210200 per year

Senior Physical Design Engineer

looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power SOC’s. What you'll... timing constraints. Debugging timing violations and rolling in functional, Timing ECO’s and netlist formal verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jul 2025