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Keywords: Design Verification Engineer - ASIC/UVM/SystemVerilog, Location: Santa Clara, CA

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Design Verification Engineer - ASIC/UVM/SystemVerilog

Azure, and Oracle. THE PERSON: We are seeking a high-impact MTS Design Verification Engineer with strong technical depth..., ownership, and the ability to drive verification closure on complex, high-performance ASIC designs. The ideal candidate brings...

Posted Date: 12 Feb 2026

Senior Design Verification Engineer

: As a Senior Design Verification Engineer, you will contribute to ASIC verification efforts for IPs, subsystems, and SoCs used... IPs to SoC product teams Required Skillset 3+ years of practical ASIC design verification experience, including...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 06 Feb 2026
Salary: $126700 - 190100 per year

Senior Design Verification Engineer

and system level. Experience using SystemVerilog and UVM. Strong experience in ASIC design verification flows and DV...Title: Senior Design Verification Engineer Location: On-site in Santa Clara, CA Job Type: Full-Time Why join Client...

Company: InterSources
Location: Santa Clara, CA
Posted Date: 01 Feb 2026

Senior ASIC Design Verification Engineer

Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet... years experience in ASIC design verification Demonstrated success in taking multiple ASIC products from concept to mass...

Location: Santa Clara, CA
Posted Date: 31 Jan 2026

IP Design Verification Engineer

your career. THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team..., industry-leading technologies to market. You will participate in design verification methodology definition as well...

Posted Date: 25 Dec 2025

ASIC Design Verification Engineer (Santa Clara, CA)

and products. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team... using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 22 Nov 2025
Salary: $126700 - 190100 per year

Principal Design Verification Engineer

components in SystemVerilog, UVM, C, and C++. Write tests in SystemVerilog, UVM, C, C++, python to test various logical features... in ASIC and SOC design blocks. Debug failures in tests and root cause issues with test environment and design. Write...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Feb 2026
Salary: $134390 - 201300 per year

Design Verification Engineer

and Accelerated Compute SOCs and IPs Develop verification test plan based on architecture and design specifications Gain... understanding of complex/random System Verilog/UVM verification environments Write and execute test cases Debug failures...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Feb 2026
Salary: $96570 - 144600 per year

ASIC Clocks Verification Engineer - New College Grad 2026

is looking for an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all aspects of GPU clocking. The team... (UVM). Experience with Design Verification, Logic Design, and Logic Synthesis. Strong coding skills in Python, Perl...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 14 Feb 2026
Salary: $116000 - 189750 per year

Infinity Fabric Verification Engineer

, complex processor architecture, digital design, and verification in general. You are a team player who has excellent... verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working...

Posted Date: 29 Jan 2026

Senior Principal Product Engineer

in ASIC/SoC design or verification. Strong hands-on experience with SystemVerilog, UVM, SVA, and verification testbench... in SystemVerilog/UVM environments. Product Definition & Roadmap Influence Gather customer requirements and translate them into use...

Company: Siemens
Location: Santa Clara, CA
Posted Date: 12 Feb 2026

Low Power ASIC Engineer - New College Grad 2026

world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue... is needed Must be fluent in Verilog, SystemVerilog, and understanding of UVM. Ways to stand out from the crowd: Prior knowledge of Low...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 07 Feb 2026
Salary: $100000 - 166750 per year