Find your dream job NOW!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: Design Verification Manager (ASIC / RTL) — 12+ Years, Location: Karnataka

Page: 1

IP Design Technical Lead/ Staff ASIC RTL Design Engineer

, or related field. 8+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects....SubCategory-ASIC-Digital-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2026-12-04 custom_fields...

Company: Synopsys
Posted Date: 30 Jan 2026

ASIC Verification, Principal Engineer

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-ASIC-Digital-Design custom_fields....SubCategory-ASIC-Digital-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2026-10-07 custom_fields...

Company: Synopsys
Posted Date: 30 Jan 2026

Architect- ASIC Verification IP Development

.SubCategory-ASIC-Digital-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2026-12-16 custom_fields... Job Description Category Engineering Hire Type Employee Job ID 13767 Remote Eligible No Date Posted 16/12/2025 Architect- ASIC Verification...

Company: Synopsys
Posted Date: 30 Jan 2026

ASIC Digital Design, Sr Staff Engineer

.SubCategory-ASIC-Digital-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2026-12-19 custom_fields...,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-ASIC-Digital-Design custom_fields...

Company: Synopsys
Posted Date: 30 Jan 2026

Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols)

. What You'll Need: Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) with 12+ years of relevant ASIC design... years of hands-on experience in ASIC design, including control path-oriented architectures, synthesis flows...

Company: Synopsys
Posted Date: 30 Jan 2026

Delivery Manager-Semiconductors

: Oversee the entire VLSI lifecycle—from RTL Design and Functional Verification to Physical Design (Synthesis, P&R) and DFT... lifecycle. You should understand 7nm/5nm nodes and the challenges of high-speed design. Experience: Typically 12–18+ years...

Company: Quest Global
Posted Date: 27 Feb 2026

Applications Engineering, Principal Engineer

and academic background considered). Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis.... What You'll Need: Masters with 10+yrs of Industry experience or equivalent At least 10+ years of experience in IP design, ASIC...

Company: Synopsys
Posted Date: 04 Mar 2026

Applications Engineering, Sr Staff Engineer

and academic background considered). Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis... such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products...

Company: Synopsys
Posted Date: 27 Feb 2026