verification of new and existing features for AMD’s memory wrappers/RTL, resulting in no bugs in the final design. Additionally...; work with RTL and memory engineers to resolve design defects and correct any test issues Review functional and code...
features for AMD’s memory wrappers/RTL, resulting in no bugs in the final design. Additionally, creating a system... of Verilog/RTL, liberty files, spice simulation, and ASIC design flows Working knowledge of AI integration into various...