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Keywords: IC Package Design Engineer, Location: Santa Clara, CA

Page: 2

Staff Applications Engineer

applications issues while supporting customer from design to production. This role involves working directly with customers, lab... Expect Understand customer’s target market, analyze, and prioritize customer design requirements, and provide feedback...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 02 Dec 2025
Salary: $102880 - 154100 per year

Senior Test Methodology Engineer

Actively participate in cross function team including Product Development Engineering, DFT, and IC design to efficiently debug...We are looking for a creative and experienced ATE Test Engineer. NVIDIA has continuously reinvented itself over three...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Nov 2025

Process engineer

to system integration requirements. Collaborate with substrate layout, IC design, and module teams to co-optimize packaging... Engine development. Experience working in cleanroom environments and advanced IC fabrication. Proficiency in design layout...

Location: Santa Clara, CA
Posted Date: 29 Oct 2025

ATE Test Engineer

Engineering, DFT, and IC design to efficiently debug product failures and implement optimal solutions. Write and maintain... experience in IC Design, application or ATE testing of VLSI. Working knowledge and hands-on experience with Advantest 93K...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Oct 2025
Salary: $100000 - 166750 per year

Advanced Packaging Engineer - SI/PI

performance, reliability, and time‑to‑market. What You Can Expect Collaborate with IC design, physical layout, assembly... engineering, and marketing to support package planning and substrate design. Build and correlate SI/PI models for advanced...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 22 Jan 2026
Salary: $97630 - 146300 per year

Sensor Engineer

devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification... tools. Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026

ATE Hardware Engineer

to do their best work. ATE/SLT hardware team provides the interface hardware of IC package testing at final test and system level test.... What you’ll be doing: Review and approve the design of test socket, thermal plunger, and other accessories related to ATE/SLT IC...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 16 Nov 2025

Advanced Packaging Modeling Expert - FEA

across a wide range of package architectures (e.g., flip-chip, fan-out, 2.5D/3D IC, chiplet-based designs, TSVs). Conduct thermal... modeling to assess heat dissipation in complex package structures, supporting thermal design optimization and advanced cooling...

Location: Santa Clara, CA
Posted Date: 18 Jan 2026