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Keywords: IP/SoC Verification Lead, Location: Bangalore, Karnataka

Page: 3

Technical Lead I - VLSI

Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis... Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture...

Company: UST
Posted Date: 04 Dec 2025

LEAD PLATFORM EMULATION ENGINEER

with BIOS/OS bring up on full X86 SOC emulation platform Proficient in IP level ASIC verification, experience working with CPU... your career. LEAD PLATFORM EMULATION ENGINEER: THE ROLE: The focus of this role is to plan, build, execute the verification...

Posted Date: 27 Nov 2025

Lead Software Engineer (Safety/MCAL)

of Verification and Validation fundamentals. Hands-on experience with integrating and bringing up daughter cards, custom IP blocks...FPGA Prototype/Emulation Lead – Platform Software & FPGA Team Location: Pune / Bangalore – India Join the RISC...

Posted Date: 23 Nov 2025

Senior Lead RTL Design Engineer

your career. LEAD ENGINEER - RTL DESIGN THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life... cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP...

Posted Date: 20 Nov 2025

Senior RTL Design Lead

specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the... or significant interest in fabric design for complex SOC . You have had significant success driving architecture, product roadmaps...

Posted Date: 20 Nov 2025

High Speed Memory/IO Circuit Lead (Mixed Signal)

your career. SMTS SILICON DESIGN ENGINEER THE ROLE: Be part of AMD’s analog/mixed signal IP design team responsible for the... design and development of next generation IOs, high speed memory (gDDRx, HBMx) and die-to-die Gbps proprietary PHY IP...

Posted Date: 18 Nov 2025

DFT (DFX) Lead Engg

Methodology/Architect/RTL execution Lead for the high-speed SERDES Phys, Next gen Memory Phys and Die-to-Die interconnect IPs.... This opportunity includes ownership of defining the DFX architecture for high-speed PHYs as well as die-to die connectivity IP designs...

Posted Date: 14 Nov 2025

Lead I - Embedded Software

for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge... debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP...

Company: UST
Posted Date: 25 Oct 2025

RTL Design (Bluetooth)-Sr Lead

interactions with system architecture, verification, SoC Design, Validation, FW, Synthesis & PD teams are required for design... expertise in designing IP and wireless sub-systems for market leading products. In this role, the candidate would be working...

Company: Qualcomm
Posted Date: 07 Jan 2026

DDRPHY Senior Staff/Staff/ Lead Digital Design Engineer

for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan... for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience...

Company: Qualcomm
Posted Date: 07 Jan 2026

Lead RTL Design Engineer

&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones. Promote... in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks...

Posted Date: 30 Dec 2025

Technical Lead I - VLSI

assigned by the client / manager as per known skills Additional Comments: JD- DV (Design Verification) • ASIC IP-level... Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis...

Company: UST
Posted Date: 04 Dec 2025

Silicon - Performance Analysis Lead/Staff Engineer

Summary: Job Overview The candidate will be part of the SOC Infrastructure IP Performance modelling and analysis team.... Candidates need to work closely with IP architects and understand the feature design/arch and define the process/methodology...

Company: Qualcomm
Posted Date: 29 Nov 2025

Senior Lead Engineer

Collaboration: Work closely with Micro-architecture, IP Design, Verification, Physical Design, and DFT teams to ensure a clean...Job Requirements Role Overview We are seeking a highly motivated and skilled SoC RTL Integration & Design Sign-off...

Company: Quest Global
Posted Date: 26 Nov 2025

RTL Lead

Collaboration: Work closely with Micro-architecture, IP Design, Verification, Physical Design, and DFT teams to ensure a clean...Job Requirements Role Overview We are seeking a highly motivated and skilled SoC RTL Integration & Design Sign-off...

Company: Quest Global
Posted Date: 13 Nov 2025

Lead Physical design, Physical Implementation, STA

your career. THE ROLE: The position will involve working with a very experienced physical design team of Server SOC... Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools...

Posted Date: 08 Nov 2025

Si GPU Functional Debug Engineer(Senior/Lead/Staff)

-Architecture) or Systems experience in GPU or CPU or multimedia IP. Candidates are expected to have experience... in debugging low level hardware Design issues, and working closely with design, verification, and software simulator teams...

Company: Qualcomm
Posted Date: 08 Nov 2025

Si GPU Functional Debug (Compute) - Sr Lead Engineer

-Architecture) or Systems experience in GPU or CPU or multimedia IP. Candidates are expected to have experience... in debugging low level hardware Design issues, and working closely with design, verification, and software simulator teams...

Company: Qualcomm
Posted Date: 06 Nov 2025

Principal Engineer, Physical Design

Job Details: Job Description: • Lead Structural Design / physical design Implementation of Custom IP and SoC designs..., reliability, and power and noise analysis. Conducts verification and signoff, including formal equivalence verification, static...

Company: Intel
Posted Date: 15 Jan 2026

Senior Technical Program Manager

will work closely with cross-functional teams across Architecture, SoC Design, IP Design, and Post-Silicon Validation to ensure... seamless IP integration and alignment with overall SoC requirements.In addition, the candidate will be responsible...

Company: Intel
Posted Date: 11 Jan 2026