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Keywords: IP DFT Verification Engineer, Location: India

Page: 4

DDRPHY Senior Staff/Staff/ Lead Digital Design Engineer

for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 07 Jan 2026

Senior Staff, RTL Design Engineer

Job Description We are seeking a highly experienced Senior Staff RTL Design Engineer to join our SoC development team.... This role involves RTL design for chiplet based power efficient chips and collaborating across architecture, verification...

Posted Date: 16 Dec 2025

Staff Synthesis & STA Engineer

, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . Staff Synthesis & STA Engineer... About the Role As a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs...

Posted Date: 12 Dec 2025

MBIST CAD/Methodology Development Engineer, Senior Lead

BIST (MBIST) CAD/Methodology Development Engineer to develop DFT methodologies for Qualcomm products in next-generation..., and deploy MBIST flow capabilities within the DFT CAD team, working closely with worldwide DFT teams, Memory IP design groups...

Company: Qualcomm
Posted Date: 04 Dec 2025

ASIC RTL Design Engineer (Sr. Lead / Staff)

Responsibilities Micro-architecture and RTL design for IP Cores / subsystems. Work in close coordination with Systems, Verification... General Summary: Job Description This role offers a position in system power management IP cores and subsystem design...

Company: Qualcomm
Posted Date: 18 Feb 2026

ASIC Engineer

& route, timing closure, power integrity, static timing verification, physical verification and equivalence checks... distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing...

Company: Cisco Systems
Posted Date: 13 Feb 2026

ASIC Engineer

& route, timing closure, power integrity, static timing verification, physical verification and equivalence checks... distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing...

Company: Cisco Systems
Posted Date: 13 Feb 2026

ASIC Engineer G10 | Physical implementation | Floor Planning | GSP & PD | Exp - 8 to 12 years | 2008104

& route, timing closure, power integrity, static timing verification, physical verification and equivalence checks... and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation...

Company: Cisco Systems
Posted Date: 12 Feb 2026

ASIC Engineer G08 | Physical implementation | Floor planning | Clock and Power distribution | Exp 4-8 Years | 2008252

& route, timing closure, power integrity, static timing verification, physical verification and equivalence checks... and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation...

Company: Cisco Systems
Posted Date: 12 Feb 2026

Principal Engineer – ASIC SoC Design

with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams. Provide technical mentorship and participate in design...Own end-to-end IP and SOC development from micro-architecture through RTL design, integration, and silicon support. Own...

Company: Micron
Posted Date: 11 Feb 2026

Principal Design Engineer

. Job Description This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry... physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work...

Posted Date: 08 Feb 2026

RTL Design Engineer

Design and develop static IP blocks using Verilog/SystemVerilog, including architecture exploration, micro-architecture... stringent timing and area requirements. Interface extensively with Design Verification (DV) teams for test plan development...

Company: Quest Global
Posted Date: 07 Feb 2026

Principal Design Engineer

. Job Description Location: Position is based in Bangalore. Job Description: We are looking for strong technical team lead for IP... Integration, subsystem creation, and QA for our SSG IP Integration and QA engineering team. The role would include working...

Posted Date: 04 Feb 2026

Principal Design Engineer

. Job Description: We are looking for strong technical team lead for IP Integration, subsystem creation, and QA for our SSG IP Integration and QA engineering team. The role.... In addition, responsibilities include ensuring various customer configurations are clean as part of verification regressions...

Posted Date: 04 Feb 2026

Design Engineer II

with DFT, CDC, LEC, or formal verification tools ✓ Knowledge of UCIE (Die-to-Die) interfaces or analog design flows... as a critical link in our design-to-customer pipeline, ensuring that every IP release meets the highest standards of quality...

Posted Date: 04 Feb 2026

Engineer- RTL

constraint generation, including clock tree specification Scan insertion and pattern generation Support IP/Design Verification... and pattern generation Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support...

Company: Quest Global
Posted Date: 27 Jan 2026

Senior Engineer- RTL

constraint generation, including clock tree specification Scan insertion and pattern generation Support IP/Design Verification... and pattern generation Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support...

Company: Quest Global
Posted Date: 27 Jan 2026

Principal ASIC Design Engineer

in semiconductor product development. Proven expertise in SoC architecture, IP selection, RTL design and verification Strong grasp... functional teams on requirements and deliverables. Lead design and verification planning and ensure design testability Perform...

Company: onsemi
Posted Date: 20 Jan 2026

Principal Engineer - SOC Clocking

with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical...

Company: Intel
Posted Date: 15 Jan 2026

Principal Engineer, Physical Design

Job Details: Job Description: • Lead Structural Design / physical design Implementation of Custom IP and SoC designs..., reliability, and power and noise analysis. Conducts verification and signoff, including formal equivalence verification, static...

Company: Intel
Posted Date: 15 Jan 2026