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Keywords: IP Design Verification Engineer, Location: San Jose, CA

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System IP Design Verification Engineer

Job Title: System IP Design Verification Engineer Position Description: Protingent Staffing has an exciting contract... System IP Design Verification Engineer opportunity for our client located in San Jose, CA. Job Description: As a Senior...

Company: Protingent
Location: San Jose, CA
Posted Date: 04 Jul 2025

IP Design Verification Engineer

- Industry experience as Design Verification Engineer Preferred Qualifications: - In-depth knowledge of UVM, System Verilog...This team is at the forefront of technological innovation, specializing in the design, development, and production...

Company: TikTok
Location: San Jose, CA
Posted Date: 09 Apr 2025

Design Verification Engineer

_ THE ROLE: We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key... processor architecture, digital design, and verification in general. You are a team player who has excellent communication...

Posted Date: 20 Jun 2025

Sr. Design Verification Engineer

solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation..., Computer Science, or a related field. ✔ 8+ years of SystemVerilog/UVM experience (IP, sub-system, or SoC level verification...

Company: Prodapt
Location: San Jose, CA
Posted Date: 06 Jun 2025

Sr. Design Verification Engineer

, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up... a highly skilled and adaptable engineer to join our dynamic team, focusing on System-on-Chip (SoC) verification. In this role...

Company: Prodapt
Location: San Jose, CA
Posted Date: 04 Jun 2025

Verification Silicon Design Engineer

’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex... processor architecture, digital design, and verification in general. You are a team player who has excellent communication...

Posted Date: 30 Apr 2025

IC Design Engineer

Job Description: IC Design Engineer Participate in IP level architectural definition including micro-architecture... designs Analyze and resolve Lint and Clock/Reset Domain crossing issues in the design Collaborate with verification team...

Company: Broadcom
Location: San Jose, CA
Posted Date: 04 Jul 2025
Salary: $120000 - 192000 per year

Senior RTL Design Engineer

_ THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive and improve... involving multiple clock domains while working with physical design to harden IP Help lead and mentor other engineers...

Posted Date: 27 Jun 2025

Senior ASIC Design Engineer (eInfochips Inc)

Position: Senior ASIC Design Engineer (eInfochips Inc) Job Description: What candidate will Be Doing: Map multi... methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...

Location: San Jose, CA
Posted Date: 10 Jun 2025

Senior Silicon Design Engineer

_ SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the Adaptive and Embedded Computing Group, you will help bring... to life cutting-edge designs. As a member of the front-end design team, you will work closely with the architecture, IP design...

Posted Date: 06 Jun 2025

Staff SRAM Circuit/Logic Design Engineer

-differentiated memory solutions tailored for advanced CPU and GPU applications. As a SRAM Circuit/Logic Design Engineer..., and physical verification. As a successful candidate, you will have a strong background in SRAM circuit and logic design...

Company: Samsung
Location: San Jose, CA
Posted Date: 28 May 2025

IC Design Engineer

Broadcom Inc. is looking for a creative and self motivated Digital IC Design Engineer to join the Data Center Solutions...-party IP. Working with cross functional teams such as Verification, Firmware and Systems Engineering to deliver detailed...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 May 2025
Salary: $101000 - 162000 per year

Senior ASIC Design Engineer (eInfochips Inc)

Position: Senior ASIC Design Engineer (eInfochips Inc) Job Description: What candidate will Be Doing: Map multi... methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...

Location: San Jose, CA
Posted Date: 15 May 2025

ASIC Design Engineer - Design & Timing Constraints

in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop... is filled or if a sufficient number of applications are received. Meet the Team Join our dynamic front-end design team...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 24 Apr 2025

ASIC Design Engineer

to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP...Technical: Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 26 Jun 2025
Salary: $60 - 70.97 per hour

MTS Silicon Design Engineer

knowledge of electronic theory. Oversee definition, design, verification, and/or documentation for ASIC/FPGA development...; Verification methodology and infrastructure for high performance IP or VLSI designs; Gate level simulation, power verification...

Posted Date: 22 Jun 2025

RTL Design Engineer - Accelerator & DPU

, performance, area, and timing goals as well as design integrity for physical implementation - Reviews the verification plan...This team is at the forefront of technological innovation, specializing in the design, development, and production...

Company: TikTok
Location: San Jose, CA
Posted Date: 04 Jun 2025

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 06 Jun 2025

Technical Leader ASIC Design - Prototyping

in block-level RTL design or block or top-level IP integration Collaborate with Software, Design, and Verification teams... is filled or if a sufficient number of applications are received. Meet the Team Join our dynamic front-end design team...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 29 Apr 2025

SMTS Analog/Mixed-Signal Design

Design Engineer to join our Bufferchip Design team in San Jose, California. Candidates will be joining some of the brightest... for verification simulations Qualifications: MS EE and 2+ years or PhD EE in CMOS analog/mixed-signal circuit design. Prior work...

Company: Rambus
Location: San Jose, CA
Posted Date: 21 Apr 2025