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Keywords: IP Verification Lead, Location: Bangalore, Karnataka

Page: 6

Staff Digital Design Engineer

in India and seeking a Staff Digital Design Engineer to lead the micro-architecture and implementation of advanced digital... closure Experience with analog IP integration and cross-domain collaboration Familiarity with automotive standards...

Company: onsemi
Posted Date: 27 Sep 2025

Staff Analog Layout Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog Layout Staff Engineer... is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security...

Company: Marvell
Posted Date: 27 Sep 2025

DFT Engineer

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation... design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer, you will impact and see the device...

Company: Amazon
Posted Date: 24 Sep 2025

Technical Director, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise... infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the...

Company: Marvell
Posted Date: 24 Sep 2025

V&V Designer

. Joining us means joining a caring, responsible, and innovative company where more than 70,000 people lead the way to greener... OF THE ROLE: As a Verification & Validation (V&V) Designer, candidate will work work with ahighly motivated team involved...

Company: Alstom
Posted Date: 23 Sep 2025

V&V Designer

. Joining us means joining a caring, responsible, and innovative company where more than 70,000 people lead the way to greener... OF THE ROLE: As a Verification & Validation (V&V) Designer, candidate will work work with ahighly motivated team involved...

Company: Alstom
Posted Date: 23 Sep 2025

DFT Director

and Hyperscaler Domains. The DFT Director's responsibilities include (but are not limited to): 1. Lead the product DFT Architecture.../micro-architecture with end-to-end DFT design and verification flow knowledge from DFT technical readiness (TR) to product...

Company: Intel
Posted Date: 22 Sep 2025

CPU/Core/Processor RTL Design Architect

as well as verification/design quality. You are a leader and team player who has excellent communication skills... of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design...

Posted Date: 14 Sep 2025

Associate III - VLSI SVP -CD

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 13 Sep 2025

Associate III - VLSI IO Design

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 12 Sep 2025

GPIO Circuit Design Engineering Manager

. For more information, visit www.gf.com. Job Summary: The GPIO Manager will lead the design, development, and delivery of GPIO IP blocks... a team of design and verification engineers to deliver GPIO IP blocks. Manage project schedules, deliverables, and resource...

Posted Date: 09 Sep 2025

Senior Principal Engineer Systems Architect

SoC and IP (design, verification, implementation) Drive continuous improvements of design flows and work methods...As a Sr. Principal Engineer Systems Architect, you will lead architecture of next-generation low-power, ML-centric...

Company: Infineon
Posted Date: 07 Sep 2025

Senior Linux & Cloud Administrator - Google Cloud Platform

and infrastructure customer issues. You will lead efforts in trouble shooting, incident handling, root cause analysis, enabling faster... understanding of TCP/IP, network interfaces, routing, DNS, DHCP, firewalls, and diagnostic tools. Security: Strong knowledge...

Company: SAP
Posted Date: 05 Sep 2025

Senior Linux & Cloud Administrator - Google Cloud Platform

and infrastructure customer issues. You will lead efforts in trouble shooting, incident handling, root cause analysis, enabling faster... understanding of TCP/IP, network interfaces, routing, DNS, DHCP, firewalls, and diagnostic tools. Security: Strong knowledge...

Company: SAP
Posted Date: 04 Sep 2025

Senior Staff to Principal Engineer - ESD Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff..., Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive...

Company: Marvell
Posted Date: 30 Aug 2025

Senior DFT Engineer

DESCRIPTION The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation.... Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning...

Company: Amazon
Posted Date: 30 Aug 2025

Senior Engineer - Sys

on the world, in a , come join us and help lead the way into the future of the intelligent edge! ABOUT THE OPPORTUNITY... protocols (IP, ICMP, ARP, etc.). Enhance existing network stack components (e.g., socket libraries, network drivers...

Company: Wind River
Posted Date: 29 Aug 2025

Staff E-TAC Engineer

We lead with personalization and choice in all of our people programs. We have disrupted the traditional view... professionals. You will regularly not just participate in, but lead technical discussions with cross-functional teams, creating...

Posted Date: 20 Aug 2025

Associate III - VLSI SRAM ACD

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 15 Aug 2025

Associate III - VLSI Analog Layout

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 15 Aug 2025