Find your dream job NOW!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: Lead Engineer -Fullchip P&R, Location: Bangalore, Karnataka

Page: 1

Lead Engineer -Block P&R

Lead engineer-Blk P&R 4+ years of professional experience to execute block-level physical design from floor planning... and routing issues. Work Experience Lead engineer-Blk P&R 4+ years of professional experience to execute block-level...

Company: Quest Global
Posted Date: 20 Feb 2026

Senior Staff/Principal CAD Engineer (P&R)

. What You Can Expect Develop and maintain leading-edge P&R flows addressing the needs of Marvell’s various Business Units..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a key CAD member of Marvell Central...

Company: Marvell
Posted Date: 21 Feb 2026

Front-End Lead Engineer (ASIC / RTL / Functional ECO)

Job Title: Front-End Lead Engineer (ASIC / RTL / Functional ECO) Location: Bengaluru (Bangalore), India Department...: Silicon Design Engineering / RTL Design Employment Type: Full-time Experience: 6 8 years (Lead Engineer) Notice Period...

Company: Best NanoTech
Posted Date: 21 Feb 2026

GPU Physical Design Engineer (Lead/Staff/Sr Staff)

, and implementation issues Develop and apply low-power implementation techniques and customized P&R strategies for GPU cores...-on experience with industry-standard P&R tools such as Synopsys ICC2 and/or Cadence Innovus Strong expertise in Static Timing...

Company: Qualcomm
Posted Date: 14 Feb 2026

Static Timing Analysis (STA) Lead, (R&D Engineering, Staff Engineer)

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields..., (R&D Engineering, Staff Engineer) Bengaluru, Karnataka, India Engineering Employee Save Job Share Jump...

Company: Synopsys
Posted Date: 30 Jan 2026

IP Design Technical Lead/ Staff ASIC RTL Design Engineer

/2026 Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the.... Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis...

Company: Synopsys
Posted Date: 30 Jan 2026

IP Design Technical Lead/ Staff ASIC RTL Design Engineer

/2025 Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the.... Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis...

Company: Synopsys
Posted Date: 30 Jan 2026

Lead Process Engineer

customers the broadest portfolio in the industry. Every day, more than 80 000 colleagues lead the way to greener and smarter...: Complete industrial documentation: industrial data sheets, IMFU (Industrial Maturity Follow-Up) Perform P-FMEA. Participate...

Company: Alstom
Posted Date: 13 Dec 2025

Lead Process Engineer

customers the broadest portfolio in the industry. Every day, more than 80 000 colleagues lead the way to greener and smarter...: Complete industrial documentation: industrial data sheets, IMFU (Industrial Maturity Follow-Up) Perform P-FMEA. Participate...

Company: Alstom
Posted Date: 13 Dec 2025

Staff Engineer - Physical Design & Signoff (Synthesis to GDS2)

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields....SubCategory-R&D-Engineering custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2026-05-19 custom_fields...

Company: Synopsys
Posted Date: 21 Feb 2026

Senior Staff R&D Engineer (Computational geometry, Image processing)

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields....Multikeywordfacets-Software"> Join our Talent Community! . Find Jobs For Where? Search Jobs Senior Staff R&D Engineer...

Company: Synopsys
Posted Date: 20 Feb 2026

Principal Engineer GPU (CUDA programming)

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields....SubCategory-R&D-Engineering custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2026-04-18 custom_fields...

Company: Synopsys
Posted Date: 19 Feb 2026

NPU/AI Processor Synthesis Sr Staff Engineer

→ Synthesis → STA → P&R. Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime). Low-Power Design... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 19 Feb 2026

R&D Engineering, Staff Engineer - Backend Technology

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields....Multikeywordfacets-Software"> Join our Talent Community! . Find Jobs For Where? Search Jobs R&D Engineering, Staff Engineer...

Company: Synopsys
Posted Date: 19 Feb 2026

Machine Learning Engineer

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields....SubCategory-R&D-Engineering custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2027-02-28 custom_fields...

Company: Synopsys
Posted Date: 15 Feb 2026

Sr Staff R&D Engineer - High Performance Core & IPs

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields....Multikeywordfacets-Software"> Join our Talent Community! . Find Jobs For Where? Search Jobs Sr Staff R&D Engineer - High...

Company: Synopsys
Posted Date: 14 Feb 2026

Staff Digital Design Engineer

and status Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog..., timing analysis and CDC, P&R, UPF and system Verilog (assertion) Solid understanding of Verilog, TCL and Perl/Python/XML...

Company: onsemi
Posted Date: 13 Feb 2026

Principal Digital Design Engineer

and status Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog... and CDC, P&R, UPF and system Verilog (assertion) Solid understanding of Verilog, TCL and Perl/Python/XML programming...

Company: onsemi
Posted Date: 13 Feb 2026

Functional Safety Application Engineer

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-Applications-Engineering custom_fields... Engineer Bengaluru, Karnataka, India Engineering Employee Save Job Share Jump to Overview Our Hardware Engineers...

Company: Synopsys
Posted Date: 12 Feb 2026

Principal Foundry Engineer –(DTCO)

,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-R&D-Engineering custom_fields.... You Are: You are a highly skilled and motivated R&D Engineer with a passion for pushing the boundaries of technology. You thrive...

Company: Synopsys
Posted Date: 12 Feb 2026