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Keywords: RTL/IP Design Lead, Location: Bangalore, Karnataka

Page: 3

Principal Engineer, Physical Design

. What You Can Expect You will work with both local and global team members on the physical design of complex chips and lead the.... Architect and lead the development of next-generation physical design methodologies and automation flows. Provide deep...

Company: Marvell
Posted Date: 31 Oct 2025

Staff Engineer Digital Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Staff Engineer... of experience. Excellent Logic design and debug skills; knowledgeable in bus protocols like AHB/AXI/I2C/UART RTL design...

Company: Marvell
Posted Date: 24 Oct 2025

Principal Engineer, Physical Design

physical design of complex chips and lead the development of advanced methodologies that enable scalable, high-performance... innovation across teams and projects. As a Principal Engineer in the Physical Design team, you will: Architect and lead the...

Company: Marvell
Posted Date: 15 Oct 2025

Senior Staff Engineer, Physical Design

at Marvell. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL/Analog... with RTL design teams to drive assembly and design closure. Provide technical direction, coaching, and mentoring to junior...

Company: Marvell
Posted Date: 15 Oct 2025

Technical Director, Physical Design

design capabilities and infrastructure in alignment with company-wide technology strategy. • Lead RTL-to-GDSII implementation... in major foundries. • Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure. • In-depth...

Company: Marvell
Posted Date: 24 Sep 2025

Associate III - VLSI IO Design

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 13 Sep 2025

GPIO Circuit Design Engineering Manager

. For more information, visit www.gf.com. Job Summary: The GPIO Manager will lead the design, development, and delivery of GPIO IP blocks... a team of design and verification engineers to deliver GPIO IP blocks. Manage project schedules, deliverables, and resource...

Posted Date: 10 Sep 2025

Lead Software Engineer (Safety/MCAL)

understanding of FPGA architecture, system-level design, and prototyping flow from RTL to implementation. Good understanding...FPGA Prototype/Emulation Lead – Platform Software & FPGA Team Location: Pune / Bangalore – India Join the RISC...

Posted Date: 23 Nov 2025

VLSI Lead L1

.com. Job Description: Job Description Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various... to Skip to Content Link Search Jobs Job Description Apply now Start Please wait... Job Title: VLSI Lead L1 Req...

Company: Wipro
Posted Date: 15 Nov 2025

DFT DFX Lead

Methodology/Architect/RTL execution Lead for the high-speed SERDES Phys, Next gen Memory Phys and Die-to-Die interconnect IPs..., and be able to independently drive tasks to completion. Key Responsiblities Lead and define PHY specific Design for Test...

Posted Date: 14 Nov 2025

VLSI Lead L1

.com. Job Description: Job Description Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various... to Skip to Content Link Search Jobs Job Description Apply now Start Please wait... Job Title: VLSI Lead L1 Req...

Company: Wipro
Posted Date: 06 Nov 2025

VLSI Lead L1

.com. Job Description: Job Description Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various... to Skip to Content Link Search Jobs Job Description Apply now Start Please wait... Job Title: VLSI Lead L1 Req...

Company: Wipro
Posted Date: 05 Nov 2025

STA Synthesis Lead

, and area (PPA) targets on SerDes PHY IPs. THE PERSON: As a senior member of the SerDes IP Physical Design team... scenarios. This role requires deep technical expertise in physical design tools and methodologies and the ability to lead...

Posted Date: 01 Nov 2025

SOC Verification Lead

your career. SOC Verification Lead WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD... together we advance_ THE ROLE: We are looking for an adaptive, self-motivative design verification engineer...

Posted Date: 24 Oct 2025

VLSI Lead - L1

.com. Job Description: Job Description Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various... to Skip to Content Link Search Jobs Job Description Apply now Start Please wait... Job Title: VLSI Lead - L1 Req...

Company: Wipro
Posted Date: 16 Oct 2025

Lead MTS Verification Engineering

Overview: Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior/Lead MTS Design..., sequences, debug of controller RTL design · Development & support of Verification environment scripting and capabilities...

Company: Rambus
Posted Date: 09 Oct 2025

DFT Lead- Bangalore- 10+ years’ experience

on various aspects of IP and SoC DFT including the DFT Architecture, Spyglass DFT, RTL implementation, Verification, Scan...We are looking for an energetic, passionate and process oriented DFT Lead who has extensive experience in planning...

Company: Angel & Genie
Posted Date: 01 Oct 2025

Technical Lead II - VLSI m-CD

contributor take ownership for any one or more task/module of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout... PT/Tempus Calibre etc. (experience with one or more tools) Technical Knowledge:a. Implement IP Spec Architecture Design...

Company: UST
Posted Date: 13 Sep 2025

Technical Lead II - VLSI MD

contributor take ownership for any one or more task/module of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout... PT/Tempus Calibre etc. (experience with one or more tools) Technical Knowledge:a. Implement IP Spec Architecture Design...

Company: UST
Posted Date: 13 Sep 2025

Si GPU Functional Debug Engineer(Senior/Lead/Staff)

debug architecture of GPU core. Preferred Qualifications 4 to 10 years of experience working in RTL Design (Micro... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 08 Nov 2025