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Keywords: RTL, Location: California

Page: 17

DDR Design Engineer

collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including... assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design...

Company: Apple
Location: Cupertino, CA
Posted Date: 31 Oct 2025

Wireless SoC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation... established design guidelines, owning all aspects of RTL development design. Integrate IP blocks and optimize memories/hard...

Company: Apple
Location: Los Angeles, CA
Posted Date: 31 Oct 2025

Wireless SoC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation... established design guidelines, owning all aspects of RTL development design. Integrate IP blocks and optimize memories/hard...

Company: Apple
Location: Los Angeles, CA
Posted Date: 31 Oct 2025

FPGA Associate (Winter 2026)

at Astranis. If you have not yet graduated from a four-year university, please apply to be an Intern. Role RTL Development... including high speed data converters, memories, MCUs Write software to interface and test RTL in hardware Collaborate closely...

Company: Astrani
Location: California
Posted Date: 31 Oct 2025
Salary: $1925 per month

Debug SoC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation... RTL ownership of debug and trace hub - development, assessment, and refinement of RTL design to target power, performance...

Company: Apple
Location: Irvine, CA
Posted Date: 31 Oct 2025

Timing Design Engineer

to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock...

Company: Apple
Location: Cupertino, CA
Posted Date: 30 Oct 2025

Sr Principal Hardware Security Engineer

, and/or RTL/gateware implementation. #LI-SM18 Qualifications: Disclaimer: Certain US customer or client-facing roles may...

Company: Oracle
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

Cellular SoC Static Timing Analysis Engineer

and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues. Own...

Company: Apple
Location: San Diego, CA
Posted Date: 30 Oct 2025

Senior Principal Digital IC Design Engineer

. Implement designs using good RTL coding and low power techniques. Collaborate with the backend team to close on synthesis... to be: Fluent in System Verilog RTL coding techniques. Familiar with modern SoC architectures and various interface technologies...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

Cellular SoC Static Timing Analysis Engineer

and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues. Own...

Company: Apple
Location: San Diego, CA
Posted Date: 30 Oct 2025

Senior DFT Engineer

vendor tools Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

CPU DFT Verification Engineer

. Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Processor Power Management Verification Engineer

with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $126800 - 190900 per year

CPU Gate Level Synthesis Engineer

-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running RTL to gate level... with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, RTL optimization...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

RFIC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Company: Apple
Location: Los Angeles, CA
Posted Date: 29 Oct 2025
Salary: $120300 - 181200 per year

SOC Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...

Company: Apple
Location: San Francisco, CA
Posted Date: 29 Oct 2025

Senior Electrical Engineer - ASIC/FPGA Mission Systems (Onsite)

architecture and design using RTL, timing closure, verification, and system integration Recommend new tools and practices... and transferable SECRET U.S. government issued security clearance is required prior to start date. RTL coding and simulation in VHDL...

Posted Date: 29 Oct 2025
Salary: $82000 - 164000 per year

WSoC PHY/MAC Validation and Integration Engineer

. Validate and characterize algorithms on real silicon alongside RTL, PHY, RF, MAC, and board designers. Bring-up...

Company: Apple
Location: San Francisco, CA
Posted Date: 29 Oct 2025

RFIC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Company: Apple
Location: Los Angeles, CA
Posted Date: 29 Oct 2025

Firmware Validation Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration...

Company: Apple
Location: Los Angeles, CA
Posted Date: 29 Oct 2025