. Job Description: Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu and/or FPGA platforms... of the synthesized FPGA RTL. Work on third-party IP integration and system-level debugging. System level RTL simulation...
development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD... Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains Familiar...