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Keywords: RTL / Design Verification Engineer, Location: Santa Clara, CA

Page: 3

Senior Analog Design Engineer

Adecco is hiring immediately for a Senior Analog Design Engineer with a local client in Santa Clara, CA. Pay...), analog circuit simulation (Spectre/ADE), and digital RTL design (System Verilog). · Knowledge of mixed mode simulation...

Company: Adecco
Location: Santa Clara, CA
Posted Date: 26 Jan 2026

Senior Analog Design Engineer

Our Client, a Materials Engineering company, is looking for a Senior Analog Design Engineer for their Santa Clara...), and digital RTL design (SystemVerilog). Knowledge of mixed mode simulation (Cadence AMS Designer) is a plus. Previous experience...

Company: ICONMA
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

Senior Circuit Design Engineer

We are now looking for a Senior Circuit Design Engineer! NVIDIA has been redefining computer graphics, PC gaming... clocking, and power management solutions. Drive the design and physical implementation of custom digital IPs from RTL...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

Senior Digital Design Engineer

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role.... What you'll be doing: As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Jan 2026

Senior ASIC Design Engineer - Hardware

We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design...-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. Support post-silicon validation...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Dec 2025

Senior ASIC Design Engineer, Memory Controller

and design including RTL design, synthesis, functional verification, and timing analysis using groundbreaking CAD tools and using...NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer, you'll...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Dec 2025

Senior C++ Software Engineer - Chip Design Tools

and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level... designs. As a software engineer, you will craft highly efficient software to automate and facilitate chip design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

Principal Mixed Signal Design Engineer

, or Mentor Graphics. Very good understanding of related areas such as RTL, Firmware, Design Verification, Design for Test... electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $165630 - 248100 per year

Digital IC Principal Design Engineer

functionality. Collaborate with verification engineer to develop exhaustive test cases to ensure successful design. Work closely.... What You Can Expect Oversee a team of engineers to develop and verify RTL design for CPU subsystems, co-processor/accelerator...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 03 Dec 2025
Salary: $146850 - 220000 per year

SOC Design Engineer

on developing the logic design, register transfer level (RTL) coding, integration, and simulation for AI System on Chips (SoCs... implementation. Key Responsibilities Develops the logic design, register transfer level (RTL) coding, simulation, and integrates...

Company: Intel
Location: Santa Clara, CA
Posted Date: 20 Feb 2026

Design Engineer - Sensors

devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification... tools. Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026

Senior Principal Engineer, Physical Design

experience in back-end physical design and verification, including significant leadership roles Proven track record of leading... understanding of current design technologies used in major foundries Strong understanding of ASIC design flow, RTL integration...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior ASIC Design Engineer

design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO...NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

Analog Design Engineer

and timing analysis, and reliability checks. Interface with cross-functional teams like RTL, Verification and Physical Design... industry. THE PERSON: Ideal candidate would be the one with not only strong circuit design knowledge, but also clear...

Posted Date: 09 Dec 2025

Senior Staff Engineer, Physical Design

verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide... across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance.... What You Can Expect You will work with a global team on both the physical design of complex chips as well as the methodology...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 05 Dec 2025
Salary: $89360 - 133900 per year

GPU HW/SW Design Architect

solutions. As HW/SW co-design engineer, you will collaborate with a strong architecture, software, and design teams... (Python, etc.) Experience in hardware modeling and design using RTL or SystemC ACADEMIC CREDENTIALS: Undergrad degree...

Posted Date: 19 Feb 2026

Lead STA & Implementation Engineer

, Access point (WIN), XR, automotive, and IoT platforms. You will collaborate closely with Architecture, RTL design, Design... verification, DFT, and physical design teams to deliver high‑quality silicon on aggressive schedules. The responsibilities include...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 25 Feb 2026

FPGA Engineer

robotic and medical systems. The engineer will own RTL design from architecture through validation, working hands...Job Title: Electrical Engineer Location: Santa Clara CA 95054 Duration: 03/16/2026 to 08/28/2026 Shift: ["Monday...

Company: LanceSoft
Location: Santa Clara, CA
Posted Date: 25 Feb 2026

Staff DFT Engineer

from RTL/netlist through post-silicon debug. In this role, you will partner closely with RTL, Physical Design, and ATE teams... violations at both block and top levels Run, analyze, and debug SpyGlass DFT/RTL checks, working with design teams to close...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 25 Feb 2026
Salary: $128000 - 189370 per year