Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV Experience... in Logic design/micro-architecture/RTL coding is a must. Must have hands on experience with design and integration of complex...
one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design..., and cultures to transform its potential into world-changing technologies and products. In the role of GPU Functional Verification...