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Keywords: RTL Design Engineer, Location: San Jose, CA

Page: 3

GNSS Software Engineer

services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Sep 2025

STA Engineer (eInfochips Inc)

to convert behavioral code (RTL) to foundry specific netlist by including proper design constraints based on product requirement...Position: STA Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Designing the integrated chips...

Location: San Jose, CA
Posted Date: 31 Aug 2025

Lead R&D Engineer - PowerArtist

-for-power platform of choice of all leading low-power semiconductor design companies for early RTL power analysis and reduction... from silicon to systems. Catalyzing the era of pervasive intelligence, we deliver design solutions, from electronic design...

Company: Ansys
Location: San Jose, CA
Posted Date: 30 Aug 2025

Principal R&D Engineer - PowerArtist

-for-power platform of choice of all leading low-power semiconductor design companies for early RTL power analysis and reduction... distributed software solutions, drive RTL power technology to solve know power challenges at lower design nodes with accurate...

Company: Ansys
Location: San Jose, CA
Posted Date: 30 Aug 2025

Power Analysis Engineer

data and build robust analysis flows for SoC designs. You will work across verification, RTL, and physical design teams.... Understanding of digital design principles with a focus on power estimation and analysis. Familiarity with RTL and gate-level...

Company: Etched
Location: San Jose, CA
Posted Date: 17 Aug 2025
Salary: $150000 - 200000 per year

GC Performance Verification Engineer

Performance Verification (GCPV) Engineer to join our team at Samsung SARC/ACL. As a GCPV Engineer, you will play a critical role... performance verification strategies to ensure that GPU designs meet performance targets and requirements You design and implement...

Company: Samsung
Location: San Jose, CA
Posted Date: 13 Aug 2025

ASIC Engineer 2

Design size/timing/power optimization via micro-architecture/RTL/Synthesis Qualifications: Masters degree desired... mixed-signal ASICs Responsibilities: Work with system architect to define micro-architecture and RTL development...

Company: Nokia
Location: San Jose, CA
Posted Date: 24 Sep 2025