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Keywords: RTL Design Engineer, Location: Santa Clara, CA

Page: 3

Implementation Timing / STA Design Engineer

timing analysis. Collaborate closely with RTL design and physical design teams to identify timing requirements... and bottlenecks. Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 08 Jun 2025
Salary: $126700 - 190100 per year

Sr. Engineer, Digital IC Design

provide automotive infotainment and electronic controllers. What You Can Expect Design and implement digital circuits..., and performance. Write and optimize low power Register Transfer Level (RTL) code, implement and simulate digital designs to ensure...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Jun 2025
Salary: $89360 - 133900 per year

Sr. SoC Design Engineer

Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis..., and formality Knowledge of high performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowledge...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 08 Jun 2025
Salary: $130600 - 160000 per year

Design Verification Engineer, Senior Staff

with architects/RTL engineers to bring-up a new architecture/micro-architecture on the verification environment. Develop testbench... in ASIC and SOC design blocks. Debug failures in tests and root cause issues with test environment and design. Write...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 May 2025
Salary: $124420 - 186400 per year

SoC Design Engineer

level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co... and Organization, and Network Processor Design and Programming. Required Skills: Digital simulator and waveform viewer. RTL...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 30 Apr 2025
Salary: $151091 - 155000 per year

Senior ASIC Synthesis Engineer

: As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks Collaboration... ASIC synthesis and integration. Deep understanding of Verilog RTL design and digital design principles. Proven...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 05 Jul 2025

Senior Power Architecture and Optimization Engineer

design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL Architect). Good verbal/written English...We are now looking for a Senior Power Architecture and Optimization Engineer! NVIDIA prides ourselves in having energy...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 05 Jul 2025

Senior Silicon Engineer

next stage in your career. Responsibilities: Own the micro-architecture specification and RTL development of design modules... OR equivalent experience. 5+ years of experience with RTL design and/or architecture experience. 5+ years of experience of DDR4~5...

Company: Microsoft
Location: Santa Clara, CA
Posted Date: 05 Jul 2025

Senior ASIC Synthesis Engineer

: As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks Collaboration... ASIC synthesis and integration. Deep understanding of Verilog RTL design and digital design principles. Proven...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Jul 2025

Senior DFT Methodology Engineer

of experience in DFT, system architecture, or RTL design. Understanding of fundamental DFT topics, such as, fault modeling, ATPG... including RTL & clocks design, STA, place-n-route and power. Strong programming and scripting skills in Perl, Python or Tcl...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Jul 2025

CPU Implementation Engineer

-offs • Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis... implementation. Description As a CPU Implementation Engineer, you will drive or participate in the following: • Work with micro...

Company: Apple
Location: Santa Clara, CA
Posted Date: 03 Jul 2025
Salary: $126800 - 190900 per year

CAD Flow Development Engineer

’s front-end ASIC software including RTL synthesis, equivalence checking, and early physical design and methodology... synthesis, physical design, formal equivalence checking. Experience in other ASIC methodologies such as RTL Lint, CDC, DFT...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Jun 2025

Principal Static Timing Analysis (STA) Engineer

(PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), RTL Design and other cross... a Principal Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Jun 2025
Salary: $124420 - 186400 per year

Senior Emulation Engineer

platforms. Your Role As an Emulation Engineer, you will: Port ASIC and IP RTL code to emulation platforms (Zebu). Build...About the Job You're Considering We are seeking an experienced Emulation Engineer with hands-on expertise in Zebu...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 19 Jun 2025

Senior Reset and Boot ASIC Engineer

. You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. Integrate modules into the overall SOC... of system-level functions like Reset or Chip Boot Solid frontend ASIC design skills, including RTL design, asynchronous...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Jun 2025

Senior DFT Engineer

DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation... breakthrough Test Architectures for reticle sized, multi-chiplet products—from RTL to verification to post-silicon ATE bring-up...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 17 Jun 2025

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... design and RTL development (SystemVerilog, Verilog). Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence...

Company: Apple
Location: Santa Clara, CA
Posted Date: 11 Jun 2025

DFX Methodology Engineer

Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure...We are now looking for a DFT Methodology Engineer! NVIDIA has continuously reinvented itself over two decades...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 07 Jun 2025

CPU Gate Level Synthesis Engineer

/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions • Early stage power... design, RTL synthesis, and physical design Preferred Qualifications The ideal candidate should possess CPU...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Jun 2025

Deep Learning Hardware Engineer

of experience. The industry experience must be in Digital Logic Design / RTL Design using System Verilog and/or Verilog... Graphic and AI group, which is part of Client Computing Group (CCG) as a Deep Learning Hardware Engineer. The Intel NPU IP...

Company: Intel
Location: Santa Clara, CA
Posted Date: 05 Jun 2025