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Keywords: RTL Engineer, Location: Santa Clara, CA

Page: 3

Testbench/Verification Engineer

The Role: Testbench/Verification Engineer for the Infinity Fabric team. The Fabric IP is a flexible and scalable high... and verification engineer with exceptional programming skills, System Verilog and UVM experience, proven experience with working...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

CPU Physical Design Engineer

design. Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025
Salary: $126800 - 190900 per year

CPU Implementation Engineer

implementation. Description As a CPU Implementation Engineer, you will drive or participate in the following: • Work with micro...-offs • Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

SR FPGA/CPLD Engineer

your career. THE ROLE: This is an exciting opportunity for an experienced Senior Hardware Development Engineer to work... development, we encourage you to apply and join our dynamic team. We are seeking a talented and experienced Engineer...

Posted Date: 05 Nov 2025

ASIC Design Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... with: - Architecture research and/or development of memory or highly interconnected system architectures. - RTL/micro-architecture...

Company: Apple
Location: Santa Clara, CA
Posted Date: 31 Oct 2025
Salary: $126800 - 190900 per year

Senior DFT Engineer

vendor tools Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure... and autonomous engineer with real passion for technology, we want to hear from you! #LI-Hybrid Your base salary...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

ASIC Design Engineer - New College Grad 2025

NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA...-architecture and design including RTL design, synthesis, functional verification and timing analysis using innovative CAD tools...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Oct 2025
Salary: $108000 - 184000 per year

Sr Principal Hardware Security Engineer

Job Category: Information Security Engineer Job Description: Department Description As part of the Oracle... Our organization is looking for a highly motivated, dedicated Senior Principal Engineer to run security architecture within a hardware...

Company: Oracle
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

CPU Processor Power Management Verification Engineer

. Description As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows: • Work closely... with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $126800 - 190900 per year

CPU Design Verification Engineer

Verification Engineer owning the verification of a certain area of functionality in a CPU design, you will have the... responsibilities as follows: • Work closely with architecture and RTL designers on verifying the functionality correctness of the...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $126800 - 190900 per year

Senior ASIC Design Engineer – Clocks IP

ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team... of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Verification Engineer

Verification Engineer owning the verification of a certain area of functionality in a CPU design, you will have the following... responsibilities: • Work closely with architecture and RTL designers on verifying the functionality correctness of the design • Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Gate Level Synthesis Engineer

groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is looking for a hardworking engineer for our CPU Gate Level..., power and area. Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Timing Engineer

implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Timing Engineer

implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Verification Engineer

Verification Engineer owning the verification of a certain area of functionality in a CPU design, you will have the following... responsibilities: • Work closely with architecture and RTL designers on verifying the functionality correctness of the design • Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU DFT Verification Engineer

. Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

Principal Engineer, Physical Design

methodologies that enable scalable, high-performance implementation. As a Principal Engineer, you will operate at the intersection... of technical depth and strategic influence, driving innovation across teams and projects. As a Principal Engineer in the Physical...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $146850 - 220000 per year