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Keywords: RTL IP Design Engineer, Location: Bangalore, Karnataka

Page: 7

NPU/AI Processor Synthesis Staff Engineer

for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality... for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain...

Company: Qualcomm
Posted Date: 26 Nov 2025

Senior SoC Director ( Bangalore )

for low power and high speed, design for test (DFT) System modeling, RTL coding, Lint / CDC checking, simulation, synthesis... roadmap decisions. Experience 12-25+ years of experience in the area of RTL design and verification of silicon...

Company: Best NanoTech
Posted Date: 15 Jan 2026

DFX Lead

your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring... architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON...

Posted Date: 15 Jan 2026

Lead MTS Analog Engineering

an exceptional PE Logic Design Engineer to join our MIC IDC Design team in Bengaluru. In this role, you will be working... Design Engineer, you’ll play a pivotal role in designing and implementing the world’s best Registered Clocking Driver (RCD...

Company: Rambus
Posted Date: 10 Jan 2026

FVCTO - Formal Verification Specialist

and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building... on world class design IPs and SOCs for Server, Client and Graphics. Use the hardware architecture design and RTL implementation...

Company: Intel
Posted Date: 08 Jan 2026

CPU/Cores Post Silicon Validation (Functional Validation)

cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional... your career. THE ROLE: The AMD Cores System Validation team is seeking a dynamic and experienced Cores Validation Engineer...

Posted Date: 01 Jan 2026

PHY Digital Lead

, Security, and Networking. What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL...-architecture design and development of SOC and associated component IP like Memory Controllers/PCIE interface/CXL interfaces...

Company: Marvell
Posted Date: 19 Dec 2025

Associate III - VLSI STA

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 17 Dec 2025

Associate III - VLSI PDN EMIR

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 17 Dec 2025

DV SV UVM_DRAM

Job Requirements ob Title Design Verification Engineer Job Description Job Summary We are seeking a talented... and detail-oriented Design Verification Engineer to join our core team. As a DV Engineer, you will play a crucial role...

Company: Quest Global
Posted Date: 16 Dec 2025

Full Chip Timing /Constraints Lead

your career. SMTS Silicon Design Engineer (Full Chip Timing /Constraints Lead) THE ROLE: As a member of the Strategic... Backend Full Chip Timing team, you will work closely with the PD architects, design leads, IP teams, Physical Design leads...

Posted Date: 11 Dec 2025

STA Synthesis Lead

your career. SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role will involve driving the physical design flow..., and area (PPA) targets on SerDes PHY IPs. THE PERSON: As a senior member of the SerDes IP Physical Design team...

Posted Date: 01 Nov 2025

Associate III - VLSI - SCL

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro...

Company: UST
Posted Date: 01 Nov 2025

Associate II - VLSI

to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development • Experience with AMD Vivado & Vitis... • Strong can-do attitude Skills: Fpga Design,Verilog RTL based IP design,System Verilog About Company: UST is a global...

Company: UST
Posted Date: 29 Oct 2025