to 64 Gbps or higher Your role and responsibilities - Lead the Architecture, Design and development of processor MMU... (Memory management unit) for high-performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate...
and sign-off criteria Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal... Strategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key...
About the Role As a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs... with large digital & analog interfaces. You'll influence implementation, guide methodology improvements, and lead small...
and problem-solving skills. Should have hands on Physical Design experience and must have handled RTL to GDS II at Top level... or Hierarchical top level for at least few tape outs. Must have led physical design team/s in the capacity of technical lead...
to ensure high-quality netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate... General Summary: Job Description Role Overview The NPU Synthesis Lead will be responsible for driving synthesis...
Business Unit (DBU) is seeking a Staff STA Engineer to lead timing sign-off and closure for complex mixed-signal SoCs..., Tempus). Implement ECOs for timing fixes and validate changes. Collaborate with RTL, physical design, and DFT teams...
, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features.... Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and do test plan, test...
, signal generators, logic analyzers, protocol analyzers, spectrum analyzers etc. · Experience with FPGA/CPLD RTL design.... · Good presentation skills required. We are looking for a motivated and enthusiastic person, at Staff level, who can lead...
Business Unit (DBU) is seeking a Senior Physical Design Engineer to lead the development of complex mixed-signal SoCs... Responsibilities Execute RTL-to-GDSII flow including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing...
Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing... Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor...
is a plus. Background in RTL Build and Design Automation is a plus. Ways to stand out from the crowd: Chip lead type of technical... in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical...
scan structures Lead efforts in performing DFT rule checks (DFT DRC) at RTL and netlist levels to ensure compliance..., ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . We are seeking a SoC DFT Lead...
enablement. Lead triage and resolution of blocking issues in coordination with architecture, validation, and debug teams... management experience and an overall industry experience of 15+ years Good understanding of SoC architecture, RTL integration...
Job Description: UST Job Title: Technical Lead II - VLSI Who we are: At UST, we help the world... verification methodologies (e.g., UVM, System Verilog, RTL). Write and debug test cases to verify functionality, performance...
netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate-level synthesis... General Summary: Role Overview The NPU Synthesis Lead will be responsible for driving synthesis and timing closure...
Title: Physical Design Lead (PnR, STA) About GlobalFoundries GlobalFoundries is a leading full-service..., or Mentor OlympusSoC) including RTL synthesis, Place and Route, parasitic extraction and static timing (Synopsys or Cadence...
sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.... Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC...
implementation tasks over management responsibilities. Key Responsibilities Lead and perform all major steps of the digital... closure. Collaborate directly with RTL and synthesis teams for timing constraint setup, synthesis refinement, and netlist...
according to technical specification and schedule in an efficient manner. Design architecture and RTL coding of digital blocks... with local technical lead. Work with test engineers to facilitate development of test hardware, test plans, and participate...
Job Description: UST Title - Technical Lead I - VLSI Who we are: At UST, we help the world’s best organizations... with RTL design teams to integrate and validate complex designs on Palladium platforms. · Perform pre-silicon validation...