your career. SENIOR SILICON DESIGN ENGINEER / MTS The Role: As a key member of the S3 SoC DFT Team, the successful candidate... Static timing analysis (STA). Experience in SOC timing closure in DFT modes and sign-off Experience with RTL quality...
and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team in Bangalore, India. The ideal... of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation (place...
your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification... level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM...
implementation. As a Principal Engineer, you will operate at the intersection of technical depth and strategic influence, driving... innovation across teams and projects. As a Principal Engineer in the Physical Design team, you will: Architect and lead the...
Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...+ years of Hardware Engineering or related work experience. Senior Technical Manager - Frontend CAD/EDA Flow Methodology...
_ SENIOR SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new... level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM...
As a Senior member in WLAN systems team you will play a key role spanning from development and implementation hardware... of reference vectors for pre-Si RTL verification of the PHY blocks and working with the PHY design team to complete design...
Job Requirements Job Description Job Title: Senior Gate-Level Simulation (GLS) Verification Engineer Location... skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon...
your career. SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role will involve driving the physical design flow..., and area (PPA) targets on SerDes PHY IPs. THE PERSON: As a senior member of the SerDes IP Physical Design team...
from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...
from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...
from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...
Overview: Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior/Lead MTS Design... Verification Engineer to join our PCIe Express IP Products team in Bangaluru, India. The successful candidate will participate...
_ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Circuit Technology Group, you will help bring to life cutting... silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate...
System on Chip (SOC) Digital Design Senior Principal Engineer, who will be responsible for end to end SOC design development... & Area) for the project Design, analyze, develop, and evaluate VLSI components Drive Design process - RTL coding, code...
Job Requirements Job Description Job Title: Senior Gate-Level Simulation (GLS) Verification Engineer Location... skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon...
Job Requirements Job Description Job Title: Senior Gate-Level Simulation (GLS) Verification Engineer Location... skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon...
of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS...