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Keywords: RTL Synthesis Engineer, Location: San Jose, CA

Page: 2

Physical IC Design Engineer

: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves...

Company: Broadcom
Location: San Jose, CA
Posted Date: 18 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves..., this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out...

Company: Broadcom
Location: San Jose, CA
Posted Date: 18 Dec 2025

Physical IC Design Engineer

: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves...

Company: Broadcom
Location: San Jose, CA
Posted Date: 10 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves..., this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out...

Company: Broadcom
Location: San Jose, CA
Posted Date: 10 Dec 2025

IC Design Engineer

Job Description: IC Design Engineer Participate in IP level architectural definition including micro-architecture... definition Perform RTL design using Verilog HDL, with an emphasis on performance and area Implement multi-power and low-power...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Nov 2025

Silicon Design Engineer

all aspects of the process flow from high-level designs to synthesis, place and route, and timing and power use. Work on problems... requires education or experience in the following: 1.Logic and circuit design; 2.RTL design or coding; 3.Verilog...

Posted Date: 25 Jan 2026

MTS Silicon Design Engineer

to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip.... Evaluate all aspects of the process flow from high-level designs to synthesis, place and route, and timing and power use. Work...

Posted Date: 25 Jan 2026

R&D ENGINEER IC DESIGN

, RTL coding, debugging and synthesis of complex functional blocks in the Traffic Manager / Memory Management Unit used... specifications Verilog RTL coding and synthesis Testplan reviews, assertions, debugging, code and functional coverage Floor...

Company: Broadcom
Location: San Jose, CA
Posted Date: 17 Jan 2026
Salary: $120000 - 192000 per year

Chip Integration Engineer

. 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static... successful candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 Nov 2025
Salary: $120000 - 192000 per year

Senior System Power Architect

, GPU, DSP, TPU) Knowledge of RTL code such as VHDL or Verilog and FPGA implementation flow (RTL, synthesis, P&R, timing... Engineer is responsible for the design and analysis of low-power hardware and software systems. This includes low-power FPGA...

Location: San Jose, CA
Posted Date: 21 Dec 2025
Salary: $175000 - 219000 per year

FPGA Prototyping Toolchain Validation & Regression Lead

your career. THE ROLE: We are seeking an engineer with strong hands-on experience in FPGA build flows, design qualification... Flow Own FPGA compile/build flows (synthesis, place & route, timing closure, bitstream generation). Develop...

Posted Date: 11 Dec 2025

Senior Custom ASIC Engineering Lead

, microarchitecture, Verilog RTL coding Front-end logic design verification, DRC, logic synthesis Knowledge of DFT methods including scan...Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas...

Company: Broadcom
Location: San Jose, CA
Posted Date: 07 Nov 2025