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Keywords: SOC Design Verification Engineer, Location: USA

Page: 12

Senior Staff RTL Design Engineer

your career. THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive... to achieve project goals and organizational growth. Work with a functional (design) verification team to meet coverage...

Posted Date: 08 Nov 2025

Digital IC design Engineer

Engineer with Marvell, you’ll be a member of the Custom compute and solutions group. Our design team works on state-of-the-art... verification. Experience in implementation/timing closure for high-speed design. Hands-on experience for all aspects of the...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

Sr. Staff Physical Design PPA Engineer

of people around the world. Come build with us! Role and Responsibilities As a Sr Staff Physical Design PPA Engineer... counterparts and SOC teams to resolve design issues pertaining to block closure, providing feedback and working together...

Company: Samsung
Location: Austin, TX
Posted Date: 07 Nov 2025

Digital, Mixed Signal IC Design Engineer, Principal

other chip companies and big tech companies, familiar names to all candidates. What You Can Expect ASIC design engineer... responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $146850 - 220000 per year

ASIC Design Engineer - Pixel IP DMA

products to millions of customers quickly. Description As a Pixel IP DMA Design Engineer in the Pixel IP team..., you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines...

Company: Apple
Location: Cupertino, CA
Posted Date: 06 Nov 2025

GPU Design Engineer - Memory Hierarchy

help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025
Salary: $126800 - 190900 per year

ASIC Engineer, Physical Design

on Chip (SoC) and IP for data center applications. ASIC Engineer, Physical Design Responsibilities Develop and own..., and drive execution Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power...

Company: Meta
Posted Date: 06 Nov 2025

GPU Design Engineer - Memory Hierarchy

help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

RFIC Design Engineer

product experience for our customers worldwide. Description As a RFIC Design Engineer, you are going to be responsible... and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test...

Company: Apple
Location: Irvine, CA
Posted Date: 31 Oct 2025

Physical Design Engineer

hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft.... Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL...

Company: Apple
Location: Beaverton, OR
Posted Date: 30 Oct 2025

ASIC Design Engineer - New College Grad 2025

NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA...-architecture and design including RTL design, synthesis, functional verification and timing analysis using innovative CAD tools...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Oct 2025
Salary: $108000 - 184000 per year

Digital IC Design Engineer Intern

, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern... verification with SystemVerilog, SystemC/C++, or UVM Experience automating tool flows Experience with embedded design Experience...

Company: Neuralink
Location: Fremont, CA
Posted Date: 29 Oct 2025
Salary: $35 per hour

RFIC Design Engineer

, Design Verification, Test and Validation, and FW/SW engineering. Description The Wireless SoC Radio Team architects..., baseband filters, phase-locked loops, crystal oscillators, wideband LDOs and bandgap references. As an RFIC design engineer...

Company: Apple
Location: Los Angeles, CA
Posted Date: 29 Oct 2025
Salary: $120300 - 181200 per year

Senior ASIC Design Engineer – Clocks IP

, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle... and ability to collaborate with multiple teams. Experience in RTL design (Verilog), verification and logic synthesis...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

RFIC Design Engineer

, Design Verification, Test and Validation, and FW/SW engineering. Description The Wireless SoC Radio Team architects..., baseband filters, phase-locked loops, crystal oscillators, wideband LDOs and bandgap references. As an RFIC design engineer...

Company: Apple
Location: Los Angeles, CA
Posted Date: 29 Oct 2025

RFIC Design Engineer

, Design Verification, Test and Validation, and FW/SW engineering. Description The Wireless SoC Radio Team architects..., baseband filters, phase-locked loops, crystal oscillators, wideband LDOs and bandgap references. As an RFIC design engineer...

Company: Apple
Location: Los Angeles, CA
Posted Date: 29 Oct 2025

Specialist, Electrical Engineer (ASIC / FPGA Design Engineer)

security. Job Title: Specialist ASIC/FPGA Design Engineer Job Code: 30424 Job Location: Herndon, VA (on-site) Schedule... countries. Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key...

Location: Herndon, VA
Posted Date: 26 Oct 2025
Salary: $90500 - 168500 per year

Senior ASIC Design Engineer - DFX

architecture, design, and verification of DFT IPs for cutting-edge SoC designs. Develop, deploy, and enhance DFT methodologies... Engineering or related field. 5+ years of hands-on experience in SoC architecture, RTL design, and verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Oct 2025

Sr. Specialist, Electrical Engineer (ASIC / FPGA Design) Engineer)

security. Job Title: Sr. Specialist ASIC/FPGA Senior Design Engineer Job Code: 30428 Job Location: Herndon, VA (on-site... countries. Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Design Engineer will be part...

Location: Herndon, VA
Posted Date: 26 Oct 2025
Salary: $104500 - 193500 per year

ASIC Design Engineer - Pixel IP DMA

products to millions of customers quickly. Description As a Pixel IP DMA Design Engineer in the Pixel IP team..., you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines...

Company: Apple
Location: Cupertino, CA
Posted Date: 25 Oct 2025