solution. As a Verification Applications Engineer, you will drive the effort to enable the verification methodology... of the big picture at the ASIC architectural and system level, and hands-on block/SoC verification experience...
WE ARE LOOKING FOR: Has knowledge of Verilog RTL design. Has knowledge of UVM verification methodology. Has knowledge of the digital design flow... of SoC. Good English in talking, presenting, and writing documents. MS/PHD degree in EE or CS. #LI-EJ1 #LI-HYBRID...