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Keywords: STA Lead, Location: Bangalore, Karnataka

Page: 3

R&D Engineering, Staff Engineer - Backend Technology

Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the... development, including PnR, STA, DRC, LVS, and EMIR analysis. Collaborating with design, CAD, and cross-functional teams...

Company: Synopsys
Posted Date: 19 Feb 2026

NPU/AI Processor Synthesis Sr Staff Engineer

+ years of Hardware Engineering or related work experience. Role Overview The NPU Synthesis Lead will be responsible... Ownership Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler...

Company: Qualcomm
Posted Date: 19 Feb 2026

Sr Staff R&D Engineer - High Performance Core & IPs

Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the..., constraints management, LEC, and STA flows. Hands-on experience with advanced process nodes (under 5nm) and complex IP...

Company: Synopsys
Posted Date: 14 Feb 2026

SOC Engineering, Staff Engineer

-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high... optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block...

Company: Synopsys
Posted Date: 07 Feb 2026

Technical Director

Job Requirements Role Summary: Lead global physical design competency development and turnkey SoC implementation... correlation across synthesis, STA, and signoff domains. PD Competency Operations: Define KPIs for competency growth, bench...

Company: Quest Global
Posted Date: 31 Jan 2026

Senior Physical Design Engineer

be doing: In this position, you will expected to lead all block/chip level PD activities. PD activities includes floor... plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work...

Company: Nvidia
Posted Date: 31 Jan 2026

Staff Digital Engineer

, you will lead the micro-architecture and design of high‑performance chips for next‑generation memory interface products... Responsibilities Lead RTL design and micro‑architecture development for memory interface digital blocks and subsystems. Own end...

Posted Date: 30 Jan 2026

Staff Digital Engineer

(MID) Business Unit. In this role, you will lead the micro-architecture and design of high-performance chips... digital logic design. Key Responsibilities Lead RTL design and micro-architecture development for memory interface digital...

Posted Date: 30 Jan 2026

Applications Engineering, Principal Engineer

Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the... time for projects. PDS are expected to possess Place & Route (physical) , Synthesis (logical and physical), STA experience...

Company: Synopsys
Posted Date: 30 Jan 2026

Staff Application Engineer

Application Engineer - ECO Timing Timing Signoff Specialist Design Closure Engineer STA/ECO Field Engineer Physical Design... is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design...

Company: Synopsys
Posted Date: 30 Jan 2026

Sr Staff Application Engineer – ECO Timing

Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the... project execution using Synopsys STA, ECO, and design implementation solutions. Partnering with customer technical managers...

Company: Synopsys
Posted Date: 30 Jan 2026

Application Engineering, Sr Staff Engineer

Timing Analysis Application Engineer PrimeTime Application Specialist STA Solutions Engineer EDA Applications Engineer... Be Doing: Providing expert-level support for PrimeTime, Synopsys' industry-leading Static Timing Analysis (STA) tool...

Company: Synopsys
Posted Date: 30 Jan 2026

Staff ASIC Engineer – DFT

, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation..., and scan STA is matched by your ability to adapt to new tools and technologies. You value open communication, inclusivity...

Company: Synopsys
Posted Date: 29 Jan 2026

NPU/AI Processor Synthesis Sr Staff Engineer

General Summary: Role Overview The NPU Synthesis Lead will be responsible for driving synthesis and timing closure... netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate-level synthesis for NPU...

Company: Qualcomm
Posted Date: 29 Jan 2026

Senior Physical Design Engineer

technology nodes, directly supporting ADI’s mission of innovation and impact. You will lead challenging floorplanning, place... detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical...

Posted Date: 29 Jan 2026

Senior Physical Design Engineer

technology nodes, directly supporting ADI’s mission of innovation and impact. You will lead challenging floorplanning, place... detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical...

Posted Date: 29 Jan 2026

Staff DFT Engineer

. This role requires deep hands-on expertise, strong technical judgment, and the ability to lead and mentor junior engineers... coverage, test time, power, area, and schedule tradeoffs DFT Implementation (End-to-End Ownership) Lead and execute: Scan...

Posted Date: 29 Jan 2026

Senior Principal Digital IC Design Engineer

and sensing technologies solve the world's most complex challenges and lead the way in creating a safer, cleaner, and smarter... in a successful international company, and you can participate in interesting international projects. What You'll Do Lead project activities...

Company: onsemi
Posted Date: 28 Jan 2026

Senior Circuit Design Engineer

correlation of logic and RAM circuits. Be a mentor/technical lead for junior team members. What we need to see: Have sound.../aging/noise analysis. Knowledge of STA, physical design and Silicon debug is a huge plus. Ability to close design to the...

Company: Nvidia
Posted Date: 26 Jan 2026

Power, Performance & Silicon Modeling Engineer

: UPF vs RTL/Netlist consistency, PA-CDC/RDC, PA-STA, LVS/DRC implications, EM/IR with multi-domain scenarios. - Lead... methodology across RTL, synthesis, P&R, STA, and verification. - Own flow features for power intent generation, validation...

Posted Date: 21 Jan 2026