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Keywords: Senior Formal Verification Engineer, Location: Santa Clara, CA

Page: 2

Digital IC design Engineer

experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

Physical Design Methodology Engineer

clock tree construction and analysis. Block and top level Formal verification, Physical Verification and chip finishing... first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The...

Posted Date: 09 Nov 2025

Distinguished Memory PHY Architect

your career. THE ROLE: This role offers a rare opportunity for a senior technical leader to shape the future of memory... as a primary responsibility. THE PERSON: You are a highly respected engineer or architect known for solving difficult problems...

Posted Date: 28 Dec 2025