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Keywords: Senior IP Logic Design Engineer, Location: Bangalore, Karnataka

Page: 3

Formal Verification Lead (DDR PHY)

your career. SMTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for a role of Senior Member of Technical Staff, a leader... passionate about driving the cutting-edge formal verification techniques for AMD’s DDR PHY IP design. The ideal candidate...

Posted Date: 07 Jan 2026