. We are looking for an experienced Emulation Engineer with strong, hands-on expertise in Mentor Veloce and familiarity with Synopsys ZeBu to support...
mature-node technologies (e.g., 22nm, 12nm). Expertise in Synopsys/Cadence RTL to GDS digital design flow. (e.g...
by VCS, Synopsys Good understanding of computer organization/architecture Should have performance verification basics...
by VCS, Synopsys Good understanding of computer organization/architecture Should have performance verification basics...
using Synopsys Design Compiler and Cadence Genus. Develop and optimize multi-mode, multi-corner (MMMC) constraints.../POCV, and derating strategies. Proficiency in EDA tools: Synopsys Design Compiler, PrimeTime, Cadence Genus, Tempus...
ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good...
with regards to physical convergence must. EDA Tools: Mentor (Calibre), Synopsys (ICV) & icc2/innovus ACADEMIC CREDENTIALS...
cycles thorugh effective use of AI and LLM. Integrate design flows with industry tools (e.g., Cadence, Synopsys, Mentor...
. * Strong expertise with industry-standard STA tools: Synopsys PrimeTime/Cadence Tempus * Solid understanding of: Timing fundamentals...
Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience on Static Timing Analysis (PrimeTime - SI), EM/IR-Drop...
triage, and issue closure across Synopsys flows (synthesis, formal, simulation). Partner on timing closure (STA... of IO peripheral protocols (example SDIO/eMMC, USB, Ethernet etc.) Hands-on proficiency with Synopsys toolchain (e.g., Design Compiler...
-on experience in protoytping and emulation flows and methodologies and with vendor flows from Synopsys, Cadence and Siemens Hands...
using Cadence/Synopsys/Siemens tool flows Strong knowledge in digital design, Verilog and System Verilog Extensive...
/prototyping using Cadence/Synopsys/Vivado tool flows Strong knowledge in digital design, Verilog and System Verilog Extensive...
with different tools from various vendors - Synopsys, Cadence and Mentor. AMD block TileBuilder and experience in lower tech nodes...
Physical Design Experience: Full flow RTL-to-GDS with signoff analysis know-how. Tool Proficiency: Experience with Synopsys...
/FlexNOC interconnect; Flash memory subsystems. Experience in using Virtual Prototype tools (ARM Fast Models, Synopsys...
-node technologies (e.g., 22nm, 12nm) and low-power design strategies and multi-clock domain designs Expertise in Synopsys...
in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools...
cores (e.g., Synopsys DWC2/3, Cadence, Mentor). Familiarity with USB device class stacks (CDC-ACM, HID, MSC, Audio, DFU...