Find your dream job NOW!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: Synthesis, Place , Location: San Jose, CA

Page: 1

Synthesis, Place & Route Sr. Architect

of Synthesis, Place and Route to work on their next-gen FPGA Software compiler. The candidate will drive the research, design... with Marketing and Field expectations. Responsibilities: Develop new algorithms for Synthesis, Place and Route Architect...

Location: San Jose, CA
Posted Date: 05 Dec 2025

Product Engineering Intern - Genus Synthesis Solution

Synthesis Solution, contributing to the evolution of synthesis and place & route technologies. Key Responsibilities... synthesis and place & route. Support internal teams and customers by troubleshooting tool usage and providing first-line...

Posted Date: 29 Oct 2025

Principal Engineer, eFPGA Place and Route

Place and Route The Group: The charter of ADI’s eFPGA team is to co-develop an industry leading heterogenous processing... suite (optimization, place and route, bitstream), reporting (area, timing, power) and debug capabilities. This software...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 03 Oct 2025

Design Implementation Engineer

Responsibilities Include: Work on Design Implementation activities related to place and route and/ or timing closure... – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification...

Company: Broadcom
Location: San Jose, CA
Posted Date: 13 Dec 2025

FPGA Prototyping Toolchain Validation & Regression Lead

Flow Own FPGA compile/build flows (synthesis, place & route, timing closure, bitstream generation). Develop...

Posted Date: 11 Dec 2025

Application Engineer Architect

in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts... to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure...

Posted Date: 11 Dec 2025

Physical IC Design Engineer

through various methods and strategies EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning and Layout...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

experience in top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesis; experience with custom clock trees.... Responsibilities include, but are not limited to the following: Execution of Physical Design, Synthesis, Physical Verification...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025

Physical IC Design Engineer

through various methods and strategies EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning and Layout...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Application Engineer

listed in Fortune magazine and Great Place to Work as one of the 2025 World's Best Workplaces™ for the tenth time... of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing The annual salary range...

Posted Date: 11 Dec 2025
Salary: $74200 - 137800 per year

Physical IC Design Engineer

through various methods and strategies EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning and Layout...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

through various methods and strategies EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning and Layout...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025
Salary: $120000 - 192000 per year

Physical IC Design Engineer

experience in top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesis; experience with custom clock trees.... Responsibilities include, but are not limited to the following: Execution of Physical Design, Synthesis, Physical Verification...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2025

Lead Application Engineer

listed in Fortune magazine and Great Place to Work as one of the 2021 World's Best Workplaces™ for the sixth time... Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing Digital design...

Posted Date: 05 Dec 2025
Salary: $102900 - 191100 per year

Lead Application Engineer

listed in Fortune magazine and Great Place to Work as one of the 2021 World's Best Workplaces™ for the sixth time... Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing The annual salary...

Posted Date: 05 Dec 2025
Salary: $102900 - 191100 per year

Senior IC Design Verification Application Engineer

and Great Place to Work as one of the World's Best Workplaces™ year after year! As an integral member of the North America..., DDR Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing Digital...

Posted Date: 22 Nov 2025

ASIC Implementation Engineer

ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test..., floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design...

Company: Broadcom
Location: San Jose, CA
Posted Date: 22 Nov 2025

Design Implementation Engineer

Candidate would be required to work on Design Implementation activities related to place and route and/ or timing... closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical...

Company: Broadcom
Location: San Jose, CA
Posted Date: 21 Nov 2025
Salary: $120000 - 192000 per year

Senior Staff Emulation Engineer - ZEBU

and verification IPs. Knowledge on areas like Synthesis, Simulation, Verification, place and route with FPGA is preferred. Knowledge... firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over...

Company: Prodapt
Location: San Jose, CA
Posted Date: 12 Nov 2025

Senior Staff Emulation Engineer - ZEBU

-on experience in emulation/simulation and verification IPs. Knowledge on areas like Synthesis, Simulation, Verification, place.... Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™...

Company: Prodapt
Location: San Jose, CA
Posted Date: 11 Nov 2025