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Keywords: System Level Test Engineer, Location: Santa Clara, CA

Page: 7

Principal DevOps Engineer - ML/AI Algorithms

DevOps Engineer - ML/AI Algorithms Developing software is great, but developing software with a purpose... is even better! As a Principal DevOps Engineer - ML/AI Algorithms, you will work on products that help people with the most precious thing...

Company: Roche
Location: Santa Clara, CA
Posted Date: 06 Dec 2025

Senior GPU Product Application Engineer

in their system, guide partners on use of AMD tools, qualification test methods, and analysis of test results. Lead the debug... on system level reliability and resiliency features Familiarity with PCIe and relevant standards. Familiarity with GPU...

Posted Date: 06 Dec 2025

Formal Verification Staff Engineer

Coverage. Design debug, Deep bug hunting. Formal test planning, Formal tools – Jasper and/or VC-formal. System Verilog... your career. THE ROLE: We are looking for an adaptive, self-motivated formal verification engineer to join our growing team...

Posted Date: 05 Dec 2025

Sensors Software Engineer

with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain... experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 04 Dec 2025
Salary: $94200 - 166900 per year

Lead Analog SerDes Architect/Design Engineer

developing key integrated circuit components the engineer must be able to work collaboratively leading block level development... from 400G today to 1.6T+ tomorrow. We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape...

Company: Intel
Location: Santa Clara, CA
Posted Date: 03 Dec 2025

FPGA Design Engineer

an experienced FPGA Design Engineer with strong expertise in Xilinx Zynq SoC/MPSoC platforms and practical experience in camera... board-level interfaces such as DDR, high-speed IOs, I2C, UART, SPI. Work closely with hardware engineers on schematics...

Location: Santa Clara, CA
Posted Date: 28 Nov 2025
Salary: $124000 - 171000 per year

Senior GPU Firmware Engineer

in their system, guide partners on use of AMD tools, qualification test methods, and analysis of test results. Lead the debug... with power management and control theory Experience working on system level reliability and resiliency features Familiarity...

Posted Date: 27 Nov 2025

Software Engineer

system software development, or significant PhD level research in the area of network routing and packet forwarding. Applied...-class software engineers to join our Extensible Operating System (EOS) software development team. As a core member of the...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 27 Nov 2025
Salary: $123000 - 191000 per year

Electrical Engineer III - (E3)

engineering. Minimum of 6 years’ experience as a system design engineer Design or modify electrical/electronic engineering... architecture design with system level knowledge, integration and testing. Must have knowledge and understanding of equipment...

Location: Santa Clara, CA
Posted Date: 26 Nov 2025
Salary: $124000 - 171000 per year

ASIC Design Verification Engineer (Santa Clara, CA)

is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The... and products. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 22 Nov 2025
Salary: $126700 - 190100 per year

Senior Optimization Engineer

Job Description: At Hitachi Energy, we are driving the transformation of the global power system to enable a sustainable energy future... markets, integrating renewables, and ensuring grid reliability in real time. As a Senior Optimization Engineer...

Company: Hitachi
Location: Santa Clara, CA
Posted Date: 21 Nov 2025

L10/L11 PDE FA Engineer(Contract)

Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level... Jobs Job Description Apply now Start Please wait... Job Title: L10/L11 PDE FA Engineer(Contract) Req Id: 104996 City: Santa Clara State/Province...

Company: Wipro
Location: Santa Clara, CA
Posted Date: 21 Nov 2025
Salary: $45000 - 110000 per year

Hardware Validation Engineer, Hyperscale Line of Business

analysis activities in support of system hardening efforts and customer escalations Analyze large datasets from test results... your mark, come join us. THE ROLE We are seeking a highly motivated Hardware Verification Engineer for Pure's Hyperscale...

Company: Pure Storage
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

R&D Software Engineer

for efficient build and test automation. Conduct system-level debugging and performance tuning. Communicate Effectively: Present... design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions...

Posted Date: 20 Nov 2025

R&D Software Engineer

Jenkins for efficient build and test automation. Conduct system-level debugging and performance tuning. Communicate.... This includes unit and system level testing to ensure reliability, security, and adherence to customer requirements. Maintain...

Posted Date: 19 Nov 2025

Analog Design Engineer

engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization... your career. THE ROLE: AMD is searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team...

Posted Date: 16 Nov 2025

Principal Engineer Software (DLP Life Cycle (SDLC)

. Job Description We are seeking a Principal Engineer to own and revolutionize our engineering velocity and developer experience. This is a high-impact... to harden our applications from the ground up. 3. Test & Quality Automation Test Automation Framework: Own the strategy...

Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $185000 - 210000 per year

Senior Design Verification Engineer

and enable reuse of block level UVM test-benches at chip level. Come up with a comprehensive verification strategy encompassing... ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 14 Nov 2025
Salary: $126700 - 190100 per year

Digital IC design Engineer

Engineer with Marvell, you’ll be a member of the Custom compute and solutions group. Our design team works on state-of-the-art... such as reviewing test plans, coverage closure, and full-chip simulation debug. Plan, scope, and time tasks with the project manager...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

Senior Mixed Signal Design Engineer

like Spectre, HSpice, Finesim, XA) Experience in crafting test bench environments for component and top level circuit...! We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 07 Nov 2025