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Keywords: System Level Test Engineer, Location: Santa Clara, CA

Page: 9

Lead Speed and Reliability Engineer - DFP

, test and deploy new chip features. The group is muti-faceted, working across SSG and other partner teams, to enable... SOL, efficient testing meeting quality benchmarks. Scope spans from datacenter to chip level. Creating productization...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 14 Jan 2026

Optomechanical Design Engineer V

micron level assembly accuracy. You are also expected to design / develop multi-fiber optical connectors and work... with external vendors to develop connector eco-system. You are also expected to be familiar with various materials used...

Location: Santa Clara, CA
Posted Date: 09 Jan 2026

Sr Staff Engineer Software (AI Security Cloud)

, through implementation and test Implement real-time security services to customers Work with PLM on new feature requirement... on envoy and web assembly Experience in designing large distributed system and web services in the cloud Deep knowledge...

Location: Santa Clara, CA
Posted Date: 08 Jan 2026

Sr Staff Engineer Software (AI Security Cloud)

, through implementation and test Implement real-time security services to customers Work with PLM on new feature requirement... on envoy and web assembly Experience in designing large distributed system and web services in the cloud Deep knowledge...

Location: Santa Clara, CA
Posted Date: 08 Jan 2026

Quality Engineer

design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions... the development of a customer-centred organization. May maintain Quality Management System (e.g., ISO9000) and support...

Posted Date: 08 Jan 2026

Quality Engineer

insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create... the development of a customer-centred organization. May maintain Quality Management System (e.g., ISO9000) and support...

Posted Date: 07 Jan 2026

Senior FPGA Design Engineer

Vivado tools Conduct board-level bring-up and system integration testing Debug complex hardware/firmware issues using logic... analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements...

Posted Date: 06 Jan 2026

Mixed Signal Design Validation Engineer

and run test scripts to optimize overall system performance Lead focused discussions with cross-functional teams..., you will be responsible for the bring-up and characterization of high-speed mixed-signal circuits, in addition to performing system validation...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 04 Jan 2026
Salary: $108000 - 184000 per year

ICE (In-Circuit Emulation) Technology and Model Development Principal Engineer

strategies, and create high-quality collateral to support comprehensive system-level validation. Enable Next-Gen Platforms... that accelerate functional validation and enable full-system integration. Key Responsibilities Architect Innovative Solutions...

Company: Intel
Location: Santa Clara, CA
Posted Date: 25 Dec 2025

Principal Engineer Software (Cloud Management)

, Collaborate and Develop highly scalable cloud native Security & Network Management System for managing devices and services... and development is a must - Experience with or familiarity of Test Driven Development and Continuous Integration...

Location: Santa Clara, CA
Posted Date: 21 Dec 2025
Salary: $200000 - 225000 per year

Principal Engineer Software (Cloud Management)

, Collaborate and Develop highly scalable cloud native Security & Network Management System for managing devices and services... and development is a must - Experience with or familiarity of Test Driven Development and Continuous Integration...

Location: Santa Clara, CA
Posted Date: 21 Dec 2025
Salary: $200000 - 225000 per year

Senior Staff Analog Design Engineer

, transistor level schematic simulations. Work with system timing designer to define sensor readout timing control. Perform the...Work on detailed transistor level design of analog and mixed signal circuits for CMOS image sensors. Oversee the floor...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 20 Dec 2025

Sensor Characterization Engineer

with analog/digital design team to troubleshoot chip/system level performance issues; Support R&D teams by providing detailed... simulation, test of circuits, analysis of noise and distortion Circuit characterization, Cadence tools for transistor level...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 20 Dec 2025
Salary: $156853 - 160000 per year

Field Application Engineer, Server Datacenter – Supermicro

. Developing, setting Up & analyzing experiments to collect data for guiding debug activities. Setting up complicated test... harnesses in Software & Hardware to collect low level debug logs. Developing scaffolding software to assist in debug activities...

Posted Date: 18 Dec 2025

Senior Cloud Applications Engineer (Backend)

, identification of code metrics, system risk analysis, software reliability analysis. ● Develop REST APIs, work on integrations... Engineering Quality and Fundamentals Testing: Strong commitment to Automated Test-Driven Development (TDD), including writing...

Company: Pure Storage
Location: Santa Clara, CA
Posted Date: 18 Dec 2025
Salary: $122000 - 184000 per year

Senior Mixed Signal Design Validation Engineer

and run test scripts to optimize overall system performance Lead focused discussions with cross-functional teams..., you will be responsible for the bring-up and characterization of high-speed mixed-signal circuits, in addition to performing system validation...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 17 Dec 2025

Principal Interconnect Micro-architect and RTL Design Engineer

, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance... and design Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets...

Posted Date: 16 Dec 2025

Sr. Technical Support Engineer, USG, Strata

strategically, and provide expert technical assistance in high-pressure situations. Your Impact Offer advanced-level technical..., and comprehensive closure summaries in the ticketing system Conduct multi-vendor troubleshooting on complex customer engagements...

Location: Santa Clara, CA
Posted Date: 13 Dec 2025
Salary: $108800 - 176000 per year

Sr. Technical Support Engineer, USG, Strata (Swing Shift)

expert technical assistance in high-pressure situations. Your Impact Offer advanced-level technical assistance... closure summaries in the ticketing system Conduct multi-vendor troubleshooting on complex customer engagements, ensuring...

Location: Santa Clara, CA
Posted Date: 13 Dec 2025
Salary: $108800 - 176000 per year

DFT Design Engineer

under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content... to: Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well...

Company: Intel
Location: Santa Clara, CA
Posted Date: 09 Dec 2025