Find your dream job NOW!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: ASIC Design Engineer, Location: Santa Clara, CA

Page: 4

RTL Engineer

, CA (onsite) About the Role Role Overview: We are looking for a highly skilled RTL Design Engineer to join our hardware... of experience in digital logic or RTL design for ASIC/SoC projects. Strong proficiency in SystemVerilog. Solid understanding...

Company: Qualitest
Location: Santa Clara, CA
Posted Date: 03 Dec 2025
Salary: $120000 - 130000 per year

Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer

Integrity (SI/PI) Engineer to lead the design, simulation, and validation of high-speed electrical interconnects and power... architects, ASIC vendors, layout, packaging, and optical teams to co-optimize performance, manufacturability, and reliability...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 27 Nov 2025

Senior Signal Integrity / Power Integrity (SI/PI) Engineer

Hardware Engineer to join our Hardware Design team at our headquarters in Santa Clara, CA. In this role, you'll work at the...-related issues. Engage with ASIC, connector, and packaging vendors to support co-design and channel optimization...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 27 Nov 2025

RTL Engineer Lead

, CA (onsite) About the Role Role Overview: We are looking for a highly skilled RTL Design Engineer to join our hardware... of experience in digital logic or RTL design for ASIC/SoC projects. Strong proficiency in SystemVerilog. Solid understanding...

Company: Qualitest
Location: Santa Clara, CA
Posted Date: 27 Nov 2025
Salary: $140000 - 160000 per year

Senior Signal and Power Integrity Engineer - Hardware

We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two... the needle! What you'll be doing: Work on crafting creative Signal Integrity solutions to complex system design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Nov 2025

Senior Timing Methodology Engineer, Custom Circuits

with 5+ years experience in ASIC Design and Timing. Proven understanding of circuit design and spice simulations. Hands..., to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Senior Timing Methodology Engineer

To See: MS (or equivalent experience) in Electrical or Computer Engineering with 3 years’ experience in ASIC Design and Timing... usage in the ASIC flow. Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Principal Technical IP Engineer

. Proficient in project management tasks required to manage 3rd party developers. Broad-based exposure to ASIC design flows..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year

Signal Integrity Engineer Intern (Cloud Platform Optics) - Master's Degree

ASIC’s with Marvell DSP’s. These components are made operational with a highly functional embedded firmware. The team... is responsible for design, verification, and validation of these integrated high speed optical components. The team performs system...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $31 - 63 per hour

Firmware Engineer Intern - BACHELOR'S Degree

and custom ASIC platforms, embedded software for SSDs, or trusted firmware stacks for hardware security modules. Other teams... As a Firmware Engineer Intern at Marvell, you could: Develop and maintain embedded firmware for advanced hardware platforms...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Nov 2025
Salary: $27 - 55 per hour

Principal Hardware Engineer, Optics

ASIC’s with Marvell DSP’s. These components are made operational with a highly functional embedded firmware. The team... is responsible for design, verification, and validation of these integrated high speed optical components. The team performs system...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Nov 2025
Salary: $143200 - 214500 per year

Firmware Engineer Intern - MASTER'S Degree

and custom ASIC platforms, embedded software for SSDs, or trusted firmware stacks for hardware security modules. Other teams... As a Firmware Engineer Intern at Marvell, you could: Develop and maintain embedded firmware for advanced hardware platforms...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Nov 2025
Salary: $32 - 64 per hour

Senior Principal Software Engineer (NGFW Platform)

. Job Description Your Career As a member of the Platform Software group at Palo Alto Networks, you will participate in the design and development... for all Next-Gen Firewall platforms. As a Platform Software Engineer, you will be expected to participate in all phases of the...

Location: Santa Clara, CA
Posted Date: 12 Nov 2025

Principal Engineer - Performance AI/ML Network Deployment Engineering

your career. THE ROLE: The Principal Engineer DC GPU AI/ML Advanced Forward Deployment and Systems Engineering is a leadership... position designed to optimize the design, roll-out and post-rollout management of AI/ML Fabrics. The candidate will be the...

Posted Date: 12 Nov 2025

Principal Test Engineer

test solutions for ASIC SoC products. Understand design-for-test strategies and IP test methods. Specify and verify test... is looking for an experienced and motivated Test Engineer. You would be part of a collaborative, dynamic and global test engineering team supporting...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $133500 - 200000 per year

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality. • Build and Test Infrastructure: Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $126800 - 190900 per year

CPU DFT Verification Engineer

verification team focusing on DFT verification. In this highly visible role, you will be at the center of a chip design effort.... Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

SR Hardware System Engineer

to Have: Experience with specific hardware technologies, such as FPGA, CPLD, ASIC, or high-speed digital design. Experience... your career. THE ROLE: This is an exciting opportunity for an experienced SR Hardware System Engineer to work on cutting-edge...

Posted Date: 28 Oct 2025

Product Engineer Intern - Master's Degree

join a high-performing team working on advanced semiconductor technologies. You’ll collaborate with ASIC Design, Applications..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Product Engineer Intern, you’ll...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 26 Oct 2025
Salary: $22 - 45 per hour

Senior Timing CAD Engineer, Applied AI

reasoning to accelerate design closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead... for EDA, semiconductor, or complex data domains .Strong background in VLSI/ASIC design — with deep understanding of timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Oct 2025