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Keywords: ASIC Design Engineer - Cache Controller, Location: Santa Clara, CA

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ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications 10 + years of full time ASIC..., and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

ASIC Design Engineer - Cache Controller

with physical design team on the timing closure of the cache subsystem. Minimum Qualifications 3+ years of full time ASIC..., and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

ASIC Design Engineer - Cache Controller

, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel... of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $126800 - 190900 per year

Senior Memory System Engineer

of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up...NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Oct 2025