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Keywords: Chip Power Integrity Engineer, Location: San Jose, CA

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Chip Power Integrity Engineer

You will fit this role if: You are an expert in full-chip power integrity analysis using state of the art tools... More specifically we are looking for a chip power integrity expert with the following hands-on know-how: Developed innovative full-chip...

Company: Broadcom
Location: San Jose, CA
Posted Date: 07 Nov 2025

Senior Hardware System Design Engineer

for signal integrity and power integrity analysis, ensuring robust performance in challenging environments. Requirements... and Cadence Allegro, with hands-on experience in schematic capture and layout. Strong understanding of power integrity concepts...

Company: Broadcom
Location: San Jose, CA
Posted Date: 05 Nov 2025
Salary: $120000 - 192000 per year

Physical Design Engineer

: Understanding of backend Cadence tools. Deep understanding of Signal Integrity and Power Integrity for High Speed designs...Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role...

Company: Broadcom
Location: San Jose, CA
Posted Date: 08 Oct 2025
Salary: $120000 - 192000 per year

Senior Staff Hardware System Design Engineer

‑bandwidth links, pushing the limits of signal integrity and timing closure. Power Delivery & Sub‑Section Design – Design robust..., constraint management, and PCB layout for high‑speed, high‑density systems. Signal Integrity & Power Delivery Mastery – Hands...

Company: Groq
Location: San Jose, CA
Posted Date: 25 Sep 2025

Packaging Design Engineer

engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost... and systems Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements...

Posted Date: 19 Sep 2025

Package Design Engineer

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading..., including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Aug 2025

SMTS Design Engineer, NVEG

of high-speed IO circuits performance, power and area optimization, chip architecture/floorplan Demonstrated experience... contributor Knowledge and understanding of SerDes, wave pipeline circuits Experience with signal/power integrity, power delivery...

Company: Micron
Location: San Jose, CA
Posted Date: 26 Oct 2025