General Summary: Job Description Role Overview The NPU Synthesis Lead will be responsible for driving synthesis... and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis...
in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical.... Good teamwork spirit and collaboration skills with team members. Experience in synthesis, physical design and DFT...
General Summary: Role Overview The NPU Synthesis Lead will be responsible for driving synthesis and timing closure... netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate-level synthesis...
design lead and is part of BDC infrastructure (NoC/Interconnect) core team Responsible for specification, design... an impact on product competitiveness, roadmap and business objectives through Design/DV/Problem Solving Lead by example...
implementation tasks over management responsibilities. Key Responsibilities Lead and perform all major steps of the digital... physical design flow, including block-level and top-level floorplanning, placement, clock tree synthesis, routing, and timing...
timing, DFT is a plus. Proficiency in scripting languages such as Perl, Python, or Tcl for automation. Excellent problem... with local technical lead. Work with test engineers to facilitate development of test hardware, test plans, and participate...
gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints... and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation...
Engineer – Memory IP Products Join a growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY... Assist customers with gate level simulations and timing closure Participate in development of Cadence documentation...