closure, with at least 2 years in NPU or AI processor design. Experience with advanced nodes (5nm/3nm), hierarchical synthesis..., and physical-aware flows. Prior tape-out experience for NPU or DSP cores. Synthesis Ownership Lead RTL-to-gate-level synthesis...
. 15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design. Experience...Synthesis Ownership Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys...
. 12+ years in ASIC synthesis and timing closure, with at least 2 years in NPU or AI processor design. Experience...Synthesis Ownership Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys...
Synthesis Ownership Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys... Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows for hierarchical and flat designs...