Role: Design Verification Engineers DDR (either IP or SoC level experience) Work Location: US Remote Position... reviews and mentor junior engineers. Required Skills: 10+ years of hands-on experience in ASIC/IP/SoC verification...
RTL verification of block and top level SOC, comfortable with all areas of SOC Design Verification engineering...-system test benches and test suites to SOC level. Achieve targeted coverage, work with design, architecture, SW, FW...
RTL verification of block and top level SOC, comfortable with all areas of SOC Design Verification engineering...-system test benches and test suites to SOC level. Achieve targeted coverage, work with design, architecture, SW, FW...
! This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, being comfortable... with all areas of SoC Design Verification engineering, with an ability to thrive in a dynamic multi-functional organization, debate...
! This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, being comfortable... with all areas of SoC Design Verification engineering, with an ability to thrive in a dynamic multi-functional organization, debate...
in technical reviews and mentor junior engineers. Required Skills: 10+ years of hands-on experience in ASIC/IP/SoC... that offers strategic talent solutions to our clients world-wide. Job Title: Design Verification Engineer DDR Duration: Full-Time Work...
with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification...++ based verification 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM...
with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification... experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience...
, Computer Science, or a related field. ✔ 8+ years of SystemVerilog/UVM experience (IP, sub-system, or SoC level verification... solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation...
, sub-system, or SoC level verification) ✔ Strong scripting skills (Python, TCL, Perl, Shell) for automation and tool..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...
features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report... that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification...
(Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL... Engineering General Summary: Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs...
enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level..., coverage collection, gate level simulations Experience with power-aware (UPF) or similar verification methodology Knowledge...
enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level..., coverage collection, gate level simulations Experience with power-aware (UPF) or similar verification methodology Knowledge...
enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level..., coverage collection, gate level simulations Experience with power-aware (UPF) or similar verification methodology Knowledge...
and validate power intent design (UPF) at SoC level Review designs and guide IP designers' power intent design ensuring it meets... SoC level low power implementation requirements Work with design verification in validating low power design featurs...
physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc. - Experience in extraction... feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level...
physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc. - Experience in extraction... feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level...
-10 years Applications Engineering experience is a plus Knowledgeable in the areas of Verification IP protocols e.g. AMBA... faster and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the...
_ THE ROLE: We are seeking a seasoned logic designer with expertise or significant interest in IP design and development... in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment...