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Keywords: Lead Engineer - RTL, Location: Bangalore, Karnataka

Page: 9

Principal Design Engineer

. Job Description Location: Position is based in Bangalore. Job Description: We are looking for strong technical team lead for IP... with existing RTL, integration of PHYs and controllers to create sub-systems, and addition of new features. In addition...

Posted Date: 04 Feb 2026

Design Verification Engineer

projects. What You'll Do Define detailed verification plans for blocks and systems Lead the verification activities... in smaller sub-teams Develop SystemVerilog/UVM environments for blocks and top-level SoCs Debug functional errors in RTL...

Company: onsemi
Posted Date: 30 Jan 2026

NPU/AI Processor Synthesis Sr Staff Engineer

netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate-level synthesis for NPU... General Summary: Role Overview The NPU Synthesis Lead will be responsible for driving synthesis and timing closure...

Company: Qualcomm
Posted Date: 29 Jan 2026

Hardware Engineer || FPGA/Design Verifcation,UVM,UMM || Exp - 7 to 11 Years

goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote... teams based in US and Italy. Your Impact Lead and mentor a team of verification engineers, driving the development...

Company: Cisco Systems
Posted Date: 26 Jan 2026

Sr. ASIC Engineer (UVM | System Verilog | Scripting) - 8+ Yrs , BLR

stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL... performance. Support testing of design in emulation. Lead all aspects of and manage the ASIC bring-up process. Minimum...

Company: Cisco Systems
Posted Date: 26 Jan 2026

ASIC Design Verification Engineer | UVM | Exp- 8+ Years

. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers... and efficient performance. Support testing of design in emulation. Lead all aspects of and manage the ASIC bring-up process...

Company: Cisco Systems
Posted Date: 26 Jan 2026

Principal ASIC Design Engineer

platform. We are seeking a seasoned Digital Design Expert to lead a Sub-System for the platform. This is a unique opportunity... functional teams on requirements and deliverables. Lead design and verification planning and ensure design testability Perform...

Company: onsemi
Posted Date: 20 Jan 2026

Post Silicon Validation Engineer

your career. THE ROLE - x86 CPU Post-Silicon Verification Lead Experience 12–15+ years in x86 CPU or high-performance... processor post-silicon validation Job Summary We are seeking an experienced x86 CPU Post-Silicon Verification Lead to drive...

Posted Date: 18 Jan 2026

Principal Engineer, Physical Design

Job Details: Job Description: • Lead Structural Design / physical design Implementation of Custom IP and SoC designs... from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow...

Company: Intel
Posted Date: 15 Jan 2026

Principal Engineer - SOC Clocking

Job Details: Job Description: Key Responsibilities: Lead the architecture, design, and integration of SoC-wide... with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical...

Company: Intel
Posted Date: 14 Jan 2026

Fellow Silicon Design Engineer

of innovation. As a Fellow-level Verification Architect, you will define and lead the verification architecture and methodology...: Establish flows that integrate firmware/driver components with RTL to validate initialization, calibration, training sequences...

Posted Date: 13 Jan 2026

Physical design Engineer

About the Role Looking for a experienced Full Chip Lead to own and drive the entire physical design flow for SoCs. This role... seamless full-chip assembly. The candidate will lead power grid architecture and implementation, and oversee end-to-end Place...

Company: Quest Global
Posted Date: 06 Jan 2026

Senior Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise... running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing...

Company: Marvell
Posted Date: 13 Dec 2025

Senior Staff Engineer, Physical Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise...: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration...

Company: Marvell
Posted Date: 13 Dec 2025

Senior Principal Engineer, Physical Design

design capabilities and infrastructure in alignment with company-wide technology strategy. Lead RTL-to-GDSII implementation..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise...

Company: Marvell
Posted Date: 13 Dec 2025

NPU / AI Processor Synthesis Engineer

to ensure high-quality netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate... General Summary: Job Description Role Overview The NPU Synthesis Lead will be responsible for driving synthesis...

Company: Qualcomm
Posted Date: 06 Dec 2025

Senior Technologist, ASIC Development Engineering

at SanDisk, as an ASIC RTL Design Engineer, you will be at the forefront of designing high-performance ASICs. By leveraging.... SanDisk, a leader in data storage solutions, is seeking talented and experienced ASIC RTL Design Engineers to join our cutting...

Company: SanDisk
Posted Date: 21 Feb 2026

Synthesis STA Expert

your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the NBIO IP Physical aware group, you will help bring..., constraint developement. Strong handson on Synthesis , STA. Good hands on conformal flow, LEC Develop feedback to RTL team...

Posted Date: 20 Feb 2026

IP Verification Architect (DDR5/GDDR/HBM/PCIe/Highspeed protocols)

your career. PMTS SILICON DESIGN ENGINEER PMTS Role Summary A PMTS is a senior technical leader responsible for driving AMD... Leadership Define crossIP protocol or microarchitecture strategies; influence architectural decisions. Lead verification...

Posted Date: 18 Feb 2026

ASIC Engineering Technical Leader

networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineer.... You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the...

Company: Cisco Systems
Posted Date: 10 Feb 2026