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Keywords: Lead RTL Design Engineer, Location: Bangalore, Karnataka

Page: 9

Staff Synthesis & STA Engineer

About the Role As a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs... on Synthesis/STA of 4+ successful tapeouts at lower geometries Familiar with digital flow design aspects RTL to GDS Proficiency...

Posted Date: 12 Dec 2025

Staff DV Engineer

Engineer About the Role As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership... and sign-off criteria Problem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal...

Posted Date: 12 Dec 2025

Staff Engineer, STA

Business Unit (DBU) is seeking a Staff STA Engineer to lead timing sign-off and closure for complex mixed-signal SoCs..., Tempus). Implement ECOs for timing fixes and validate changes. Collaborate with RTL, physical design, and DFT teams...

Posted Date: 06 Dec 2025

Senior ASIC Engineer, Switch SoC

is a plus. Background in RTL Build and Design Automation is a plus. Ways to stand out from the crowd: Chip lead type of technical...We are currently seeking an expert SOC Design and Integration Engineer with strong design fundamentals to work...

Company: Nvidia
Posted Date: 04 Dec 2025

Emulation Engineer

Compile and Build emulation model from delivered RTL Integrate different transactor on Zebu Run sanity check Port... Hands on experince with Zebu Ability to lead Sub System deployment on zebu Good knowledge of AXI,OCP,JTAG,UART...

Company: Quest Global
Posted Date: 07 Feb 2026

Principal Hardware Engineer

with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip..., and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely...

Company: Cisco Systems
Posted Date: 06 Feb 2026

NPU/AI Processor Synthesis Sr Staff Engineer

for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality... netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate-level synthesis for NPU...

Company: Qualcomm
Posted Date: 29 Jan 2026

Formal Verification Engineer

closely with architects, RTL designers, and validation teams. Key Responsibilities Formal Verification & Proof Development... comprehensive formal verification plans: scope, coverage goals, strategy, and proof approaches. Lead ROI analysis to balance formal...

Posted Date: 29 Jan 2026

Sr. ASIC Engineer (UVM | System Verilog | Scripting) - 8+ Yrs , BLR

performance. Support testing of design in emulation. Lead all aspects of and manage the ASIC bring-up process. Minimum... and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised...

Company: Cisco Systems
Posted Date: 26 Jan 2026

Post Silicon Validation Engineer

your career. THE ROLE - x86 CPU Post-Silicon Verification Lead Experience 12–15+ years in x86 CPU or high-performance... processor post-silicon validation Job Summary We are seeking an experienced x86 CPU Post-Silicon Verification Lead to drive...

Posted Date: 18 Jan 2026

Principal Engineer - SOC Clocking

Job Details: Job Description: Key Responsibilities: Lead the architecture, design, and integration of SoC-wide... with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical...

Company: Intel
Posted Date: 15 Jan 2026

NPU / AI Processor Synthesis Engineer

flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams... to ensure high-quality netlists for advanced technology nodes. Key Responsibilities Synthesis Ownership Lead RTL-to-gate...

Company: Qualcomm
Posted Date: 06 Dec 2025

Staff Engineer, DFT Engineering

scan structures Lead efforts in performing DFT rule checks (DFT DRC) at RTL and netlist levels to ensure compliance... understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow...

Posted Date: 03 Dec 2025

Architect- ASIC Verification IP Development

is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design... Engineer with a passion for developing functional verification solutions for RTL based IP Cores. You are experienced...

Company: Synopsys
Posted Date: 30 Jan 2026

Senior Manager SOC and ASIC execution

your career. SENIOR MANAGER SILICON DESIGN ENGINEER THE ROLE (SOC Lead): Drive and lead end-to-end SOC/ASIC execution working..., Power intent design, RTL Quality checks, Clock, Reset, Fuses, Synthesis, Timing Analysis, Design Partitioning, PPA...

Posted Date: 21 Jan 2026

Associate III - VLSI STA

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... Knowledge Examples: Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of – RTL...

Company: UST
Posted Date: 17 Dec 2025

Associate III - VLSI PDN EMIR

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... Knowledge Examples: Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of – RTL...

Company: UST
Posted Date: 17 Dec 2025