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Keywords: Memory/DDR IP Verification Engineer, Location: Austin, TX

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Memory/DDR IP Verification Engineer

your career. THE ROLE The AMD UMC Team, part of the MSIP organization, is seeking a Memory/DDR IP Verification Engineer..., graphics, and semi-custom applications. In this role, you will contribute to all phases of IP verification, including...

Location: Austin, TX
Posted Date: 12 Mar 2026

Memory Systems Design Engineer Client and Graphics Platform Engineering

for DDR/LPDDR/GDDR Memory interface IP. Lead Pre-Silicon engagement preparing test plans, reviewing simulation results... your career. THE ROLE: An exciting opportunity for a memory systems design engineer within the client and graphics platform...

Location: Austin, TX
Posted Date: 19 Feb 2026

Design Verification Engineer

your career. THE ROLE: We are seeking a motivated and detail-oriented Verification Engineer to join our DDR PHY IP development... team. As an entry-level engineer, you will play a key role in verifying high-performance DDR PHY intellectual property used...

Location: Austin, TX
Posted Date: 13 Feb 2026

Design Verification Engineer

for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR... your career. THE ROLE: We are looking for an experienced Verification Engineer to join our team as a Technical Lead...

Location: Austin, TX
Posted Date: 12 Feb 2026

Design Verification Engineer

for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR... your career. THE ROLE: We are looking for an experienced Verification Engineer to join our team as a Technical Lead...

Location: Austin, TX
Posted Date: 12 Feb 2026

Staff Silicon Design Engineer

your career. THE ROLE: We are searching for a senior RTL engineer to join the DDR PHY design team. This is an exciting... next generation of high-speed DDR and inter-chip IO IP for AMD’s graphics and semi-custom products. THE PERSON: The...

Location: Austin, TX
Posted Date: 11 Feb 2026

Principal Firmware Engineer

. Job Description Be part of the Cadence DDR PHY IP Front End Design team responsible for - Develop firmware for DDR5 PHY using... on Microcontrollers. Responsible for collaborating with hardware designers and memory subsystem architects to derive training...

Location: Austin, TX
Posted Date: 21 Feb 2026