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Keywords: Memory PHY RTL Design Engineer, Location: Santa Clara, CA

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Memory PHY RTL Design Engineer

your career. THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware... design for memory I/O PHY Digital Architecture development from pathfinding, coding, verification to physical implementation...

Posted Date: 13 Nov 2025

ASIC Design Engineer

. - Knowledge of high-performance memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram... engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 31 Oct 2025
Salary: $126800 - 190900 per year

Analog Design Engineer

for memory interface PHY's in cutting edge FinFet technology nodes. Responsible for circuit design, layout quality, electrical... and implementation of high speed and high precision memory interface PHY circuits for DDR, LPDDR and GDDR. This team owns a wide variety...

Posted Date: 09 Dec 2025