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Keywords: Physical Design Timing Engineer (STA), Location: San Jose, CA

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Physical Design Timing Engineer (STA)

The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets... (crosstalk), and IR-drop aware STA Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios...

Company: Broadcom
Location: San Jose, CA
Posted Date: 18 Dec 2025
Salary: $120000 - 192000 per year

Principal Static Timing Analysis (STA) Engineer

Principal Static Timing Analysis (STA) Engineer About the Role: We are seeking a highly experienced Principal STA..., you will own complex blocks and full-chip STA analysis, and act as a technical authority within the Physical Design team...

Location: San Jose, CA
Posted Date: 20 Feb 2026

ASIC Design Technical Leader – Design & Timing Constraints Focus

. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints... for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 26 Jan 2026

Physical Design Engineer (ASIC / SoC) in San Jose, CA

across emerging technologies. As a hands-on Physical Design Engineer, you’ll own projects from feasibility through tape-out..., and timing optimization Execute sign-off activities including RC extraction, STA, IR-drop analysis, and physical verification...

Posted Date: 12 Feb 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

→ Synthesis → STAPhysical Design → Tape-out Experience writing and debugging SDC timing constraints, including multi-cycle... in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt...

Posted Date: 21 Feb 2026

Senior Technical Staff Engineer - Design for Test

with different teams within the FPGA business unit spanning architecture, ASIC design, verification, physical implementation... of Verilog, synthesis, physical implementation and STA Good understanding of verification methodology Preferred Skills...

Company: Microchip
Location: San Jose, CA
Posted Date: 11 Feb 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

development lifecycle—from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical... checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation. Timing Closure...

Posted Date: 08 Feb 2026

ASIC/SoC Design Engineer

, verification, physical design integration, and post-silicon validation. Integrate complex configuration blocks into full-chip... for configuration/control paths Work with the Physical Design team to ensure proper implementation of the design PREFERRED...

Posted Date: 21 Feb 2026

Design Implementation Engineer

in place and route and/or timing (constraints, STA) can be considered for this position. Proficient in design implementation...Responsibilities Include: Work on Design Implementation activities related to place and route and/ or timing closure...

Company: Broadcom
Location: San Jose, CA
Posted Date: 15 Jan 2026

Design Implementation Engineer

expertise in place and route and/or timing (constraints, STA) can be considered for this position. Proficient in design...Responsibilities Include: Work on Design Implementation activities related to place and route and/ or timing closure...

Company: Broadcom
Location: San Jose, CA
Posted Date: 14 Jan 2026

Senior ASIC Engineer - SDC

/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels... to first customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 26 Jan 2026