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Keywords: Principal Engineer, RTL ASIC Design, Location: Bangalore, Karnataka

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Principal ASIC / RTL Design Engineer

, regarding overall project development progress and status Solid understanding of RTL design, CDC, ASIC synthesis, timing...Job Category: Engineering, Design Degree Level: Bachelors Job Description: OnSemi is seeking a Principal Digital...

Company: onsemi
Posted Date: 24 Jan 2026

Sr Principal ASIC / RTL Design Engineer

years of experience in RTL design/development Experience in working and leading Digital Design, Architecture and ASIC/Mixed... project development progress and status Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R...

Company: onsemi
Posted Date: 24 Jan 2026

Sr Principal ASIC / RTL Design Engineer

and motivated Senior Digital IC Design Engineer with over 5 years of experience in digital design and proven expertise in memory IP... constraints, and test features. Perform RTL design, lint, CDC, and synthesis for digital logic blocks interacting with embedded...

Company: onsemi
Posted Date: 06 Feb 2026

Senior Principal Engineer, RTL ASIC Design

Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation... collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the...

Company: Marvell
Posted Date: 09 Jan 2026

Principal Engineer, RTL ASIC Design

with System Verilog assertions. Well-versed in all stages of the ASIC design flow (including specification, architecture... that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company...

Company: Marvell
Posted Date: 07 Jan 2026

ASIC Principal Design Engineer

ASIC Principal Design Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily... timing fixes What you need to bring: Required Skills: Strong Verilog RTL coding skills Knowledge of Synopsys Design...

Posted Date: 09 Feb 2026

Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols)

Eligible No Date Posted 26/11/2025 Alternate Job Titles: Principal Engineer - ASIC Digital Design IP Development (Ethernet....Multikeywordfacets-Hardware"> Join our Talent Community! . Find Jobs For Where? Search Jobs Principal Engineer - ASIC Digital...

Company: Synopsys
Posted Date: 30 Jan 2026

Principal ASIC Design Engineer

in semiconductor product development. Proven expertise in SoC architecture, IP selection, RTL design and verification Strong grasp... centers. Its modular architecture simplifies design, reduces system costs, and accelerates time-to-market. All products...

Company: onsemi
Posted Date: 20 Jan 2026

Principal ASIC Digital Verification Engineer- IP Development

/2025 Job Title: ASIC Digital Verification- Principal Engineer We Are: At Synopsys, we drive the innovations...,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-ASIC-Digital-Design custom_fields...

Company: Synopsys
Posted Date: 30 Jan 2026

ASIC Verification, Principal Engineer

technological innovation. You Are: You are an experienced and innovative ASIC Digital Design Principal Engineer with a passion...,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-ASIC-Digital-Design custom_fields...

Company: Synopsys
Posted Date: 29 Jan 2026

Principal Design Engineer

flows like RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT, lint... would include working with existing RTL, integration of PHYs and controllers to create sub-systems, and addition of new features...

Posted Date: 04 Feb 2026

Principal Design Engineer

flows like RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT, lint... with existing RTL, integration of PHYs and controllers to create sub-systems, and addition of new features. In addition...

Posted Date: 04 Feb 2026

Senior Principal Digital Design Engineer

. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group..., CAN protocols The candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing...

Company: onsemi
Posted Date: 13 Feb 2026

Sr Principal Digital Design Engineer

Job Category: Engineering Degree Level: Masters Job Description: OnSemi is seeking a Sr. Principal Digital design... The candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis...

Company: onsemi
Posted Date: 13 Feb 2026

Principal Digital Design Engineer

and status Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog... overall project development progress and status Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis...

Company: onsemi
Posted Date: 13 Feb 2026

Principal Engineer, Physical Design

from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow...Job Details: Job Description: • Lead Structural Design / physical design Implementation of Custom IP and SoC designs...

Company: Intel
Posted Date: 15 Jan 2026

Senior Principal Engineer, Physical Design

in major foundries. Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure. In-depth... design capabilities and infrastructure in alignment with company-wide technology strategy. Lead RTL-to-GDSII implementation...

Company: Marvell
Posted Date: 13 Dec 2025

Applications Engineering, Principal Engineer

and academic background considered). Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis..., Principal Engineer Bengaluru, Karnataka, India Engineering Employee Save Job Share Jump to Overview Our Hardware...

Company: Synopsys
Posted Date: 05 Mar 2026

Applications Engineering, Principal Engineer

should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing) RTL to GDSII full flow experience..., Principal Engineer Bengaluru, Karnataka, India Engineering Employee Save Job Share Jump to Overview Our Hardware...

Company: Synopsys
Posted Date: 30 Jan 2026

Principal SOC DV Engineer

developed ASIC test FW on RTL simulations, Netlist simulations and Emulation platforms. Bachelors/Masters in Engineering... Interact with Architecture/Design/FW teams to identify actual FW implementation and perform verification accordingly Develop...

Company: Micron
Posted Date: 05 Feb 2026