infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology..., porting and maintaining System Verilog Assertions Development of tools for Design and Verification support Debug failures...
/Experience: 1-2 years of strong experience in design verification Strong knowledge of HDLs like Verilog, System Verilog... Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC...