Title: Principal Engineer (RTL Expert) Location: Sunnyvale, CA (Onsite role) Duration: Full-time/Perm... Required: Looking for RTL expert with 800G to 1.6T Ethernet controller expertise. Knowledge of Ultra Ethernet is a big plus. Must have 10-15...
Role: Principal Engineer AI Hardware Modeling Location: Mountain View, CA Project description The Principal... for an engineer with deep expertise in hardware modeling, emulation, and hardware-software co-design. This role provides expert-level...
Principal VLSI Design Engineer, Sunnyvale, CA This role has been designed as ‘’Onsite’ with an expectation... preferred). Expert in RTL coding in Verilog or SystemVerilog, assertions and functional coverage Strong knowledge of digital...
Principal VLSI Design Engineer, Sunnyvale, CA This role has been designed as ''Onsite' with an expectation... preferred). Expert in RTL coding in Verilog or SystemVerilog, assertions and functional coverage Strong knowledge of digital...
Principal VLSI Design Engineer, Sunnyvale, CA This role has been designed as ‘’Onsite’ with an expectation... preferred). Expert in RTL coding in Verilog or SystemVerilog, assertions and functional coverage Strong knowledge of digital...
Role: Principal Engineer, AI Hardware Modeling Work location: Mountain View, CA Job Description: "The Principal... for an engineer with deep expertise in hardware modeling, emulation, and hardware-software co-design. This role provides expert-level...
Principal Physical Design Engineer This role has been designed as ‘Hybrid’ with an expectation that you will work... with HPE. Job Description: Job Description: Physical Design Flow and P&R Development Engineer (Innovus / Fusion Compiler...
"Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential TMR ID: UXT9RL Role: Principal Engineer, AI Hardware... for an engineer with deep expertise in hardware modeling, emulation, and hardware-software co-design. This role provides expert-level...
Position: Physcial Design Engineer III Job Description: What candidate will Be Doing: Principal Accountabilities... level place and route assignments from Netlist through GDS flow Perform full chip implementation of complex SoCs (RTL...