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Keywords: R&D Intern - FPGA/RTL Design Engineer, Location: Irvine, CA

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R&D Intern - FPGA/RTL Design Engineer

connectivity, including video and high-bandwidth data. Job Description THE OPPORTUNITY The InternFPGA/RTL Design Engineer... architecting for wireless communication projects. RTL coding, simulation, and test bench development. FPGA synthesis and timing...

Location: Irvine, CA
Posted Date: 22 Feb 2026
Salary: $28.6 - 33.8 per hour